Design and Simulation of Novel 11-level Inverter Scheme with Reduced Switches

R. Palanisamy (SRM Institute of Science and Technology)
Gaurav Singh (SRM Institute of Science and Technology)
Priyanka Das (SRM Institute of Science and Technology)
D. Selvabharathi (SRM Institute of Science and Technology)
Sourav Sinha (SRM Institute of Science and Technology)
Arnab Nag (SRM Institute of Science and Technology)

International Journal of Electrical and Computer Engineering
Vol 8, No 5: October 2018

This work recommends the performance of coupled inductor based novel 11-level inverter with reduced number of switches. The inverter which engender the sinusoidal output voltage by the use of split inductor with minimised total harmonic distortion (THD). The voltage stress on each controlled switching devices, capacitor balancing and switching losses can be reduced. The proposed system which gives better controlled output current and improved output voltage with moderate THD value. The switching devices of the system are controlled by using multicarrier sinusoidal pulse width modulation algorithm by comparing the carrier signals with sinusoidal signal. The simulation and experimental results of the proposed 11-level inverter system outputs are established using matlab/Simulink and dsPIC microcontroller respectively.