High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

Veepsa Bhatia (Indira Gandhi Delhi Technical University for Women)
Neeta Pandey (Indira Gandhi Delhi Technical University for Women)
Asok Bhattacharyya (Indira Gandhi Delhi Technical University for Women)

International Journal of Electrical and Computer Engineering
Vol 6, No 1: February 2016

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.