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Veepsa Bhatia
Indira Gandhi Delhi Technical University for Women
Computer Science & IT Electrical & Electronics Engineering

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High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology Veepsa Bhatia; Neeta Pandey; Asok Bhattacharyya
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 1: February 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (475.517 KB) | DOI: 10.11591/ijece.v6i1.pp90-98

Abstract

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.
Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks Veepsa Bhatia; Neeta Pandey; Asok Bhattacharyya
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 1: February 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (689.154 KB) | DOI: 10.11591/ijece.v6i1.pp320-329

Abstract

Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance.  While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.
Co-Authors Asok Bhattacharyya Asok Bhattacharyya Neeta Pandey Neeta Pandey