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All Journal International Journal of Electrical and Computer Engineering
Asok Bhattacharyya
Indira Gandhi Delhi Technical University for Women
Computer Science & IT Electrical & Electronics Engineering

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High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology Veepsa Bhatia; Neeta Pandey; Asok Bhattacharyya
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 1: February 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (475.517 KB) | DOI: 10.11591/ijece.v6i1.pp90-98

Abstract

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.
Co-Authors Neeta Pandey Veepsa Bhatia