<![CDATA[Dump Accumulator on RFID system built from Register and counter. On the block counter requires a series of NAND, Half Adder, and D flip flop. This paper compares the two discrete schematic designs for a combination of NAND 4 logic input gates. Schematic design made work at 5Mhz frequency and maximum voltage of 3.3volt with Lt spice XVII application software. The first design uses the AND and NAND 2 logic gate combined inputs. The second design uses a NAND 4 logic input gate that is combined from a horizontally arranged (PMOS) and vertical (NMOS) CMOS component. Overall the second design has many advantages over the first design. The simulation results of the two designs show that the first design has advantages in the test of time (speed test), T fall is balanced with T rise is 12ns, total time required 24ns. But power dissipation is large (55,43pW). While in the second design, it has a few advantages of small CMOS components, a simpler schematic design, a small power dissipation (11.15pW), speed at T fall (20ns) larger than T rise (2ns), total time required 22ns. Keywords: gerbang logika NAND, Desain diskrit, Trise, Tfall, Power Dissipation]]>
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