Automatic generation of user-defined test algorithm description file for memory BIST implementation

Aiman Zakwan Jidin (Universiti Malaysia Perlis, Universiti Teknikal Malaysia Melaka)
Razaidi Hussin (Universiti Malaysia Perlis)
Lee Weng Fook (Emerald System Design Center)
Mohd Syafiq Mispan (Universiti Teknikal Malaysia Melaka)
Loh Wan Ying (Universiti Malaysia Perlis)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 11, No 2: July 2022

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.