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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Aiman Zakwan Jidin
Universiti Malaysia Perlis, Universiti Teknikal Malaysia Melaka
Economics, Econometrics & Finance

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Automatic generation of user-defined test algorithm description file for memory BIST implementation Aiman Zakwan Jidin; Razaidi Hussin; Lee Weng Fook; Mohd Syafiq Mispan; Loh Wan Ying
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp103-114

Abstract

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.
Co-Authors Lee Weng Fook Loh Wan Ying Mohd Syafiq Mispan Razaidi Hussin