<![CDATA[Meeting aggressive time-to-market and high-quality requirements for complex storage controller System-on-Chip (SoC) designs is an increasingly difficult task for the semiconductor industry. Verification consumes a significant portion of the design cycle in SoC design, with regression serving as the primary bottleneck that hinders time to market. Customary verification methodologies reactively locate high-risk design areas after the fact, followed by costly debug iterations and lengthy validation runs. However, machine learning-based predictive analytics can be used to analyze the trends in past verification runs, thus enabling the identification of the areas most prone to regression before they occur. The framework uses gradient-increasing decision trees trained on a large corpus of coverage metrics, structural design features, patterns of modification, and temporal failure histories learned across generations of controllers. Signal extraction across heterogeneous sources, including regression databases, coverage repositories, design revision history, and bug tracking systems, is a key part of this process. Benchmarking of enterprise-quality NVMe controllers shows that the proposed approach considerably reduces regression detection time and verification time while achieving the same coverage effectiveness. The deployed approach is compatible with Universal Verification Methodology workflows, offering visual dashboards and automated test prioritization methods that complement human intuition, rather than simply automating them. Our cross-architecture transfer learning results positively affect the generalization of the models across architectures and help speed up knowledge transfer to other projects in the organization. Our empirical results help challenge the status quo of coverage-driven planning and show that risk-based prioritization can effectively address the increasing complexity of modern semiconductor design]]>
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