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International Journal of Reconfigurable and Embedded Systems (IJRES)
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 5 Documents
Search results for , issue "Vol 1, No 2: July 2012" : 5 Documents clear
FPGA Implementation of a 64-Bit RISC Processor Using VHDL Imran Mohammad; Ramananjaneyulu K
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (277.105 KB) | DOI: 10.11591/ijres.v1.i2.pp59-66

Abstract

In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.
AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key Samir El Adib; Naoufal Raissouni
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (237.701 KB) | DOI: 10.11591/ijres.v1.i2.pp67-74

Abstract

Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.
FPGA Based a PWM Technique for Permanent Magnet AC Motor Drives Tole Sutikno; Nik Rumzi Nik Idris; Nuryono Satya Widodo; Auzani Jidin
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (413.193 KB) | DOI: 10.11591/ijres.v1.i2.pp43-48

Abstract

The permanent magnet AC motor trapezoidal (BLDC motor) is not strictly DC motor, which uses a pulsed DC fed to the stator field windings to create a rotating magnetic field. Therefore, the motor needs an electronic commutation to provide the rotating field. A pair of switches must be turned on sequentially in the correct order to energize a pair of windings. If the incorrect order is applied, then the BLDC motor will not operate properly. This paper presents a smart guideline to ensure that the order to energize a pair of windings is correct. To ensure the guideline, FPGA based a simple commutation state machine scheme to control BLDC motor is presented. The experiment results have shown that the guideline is correct. The commutation scheme was successfully realized using Altera's APEX20KE FPGA to control BLDC motor in both of forward/reverse rotations or forward/reverse regenerative braking properly.
Vehicle Accident Automatic Detection and Remote Alarm Device Varsha Goud
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (130.769 KB) | DOI: 10.11591/ijres.v1.i2.pp49-54

Abstract

The Rapid growth of  technology and infrastructure has made our lives more easy . The advent of technology has also increased the traffic hazards and the  road  accident take place frequently which causes huge loss of life and property because of the poor emergency facilities. Our project will provide an optimum solution to this draw back. An accelerometer can be used in a car alarm application so that dangerous driving can be detected . It can be used as a crash or rollover detector of the vehicle during and after a crash. With signals from an accelerometer, a severe accident can be recognized. According to this project when a vehicle meets with an accident immediately Vibration sensor will detect the signal or if a car rolls over, an Micro electro mechanical system(MEMS) sensor will detects the signal and sends it to ARM controller. Microcontroller sends the alert message through the GSM MODEM including the location to police control room or a rescue team. So the police can immediately trace the location through the GPS MODEM, after receiving the information. Then after conforming the location necessary action will be taken. If the person meets with a small accident or if there is no serious threat to anyone`s life, then the alert message can be terminated by the driver by a switch provided in order to avoid wasting the valuable time of the medical rescue team. This paper is useful in detecting the accident precisely by means of both vibration sensor and Micro electro Mechanical system(MEMS) or accelerometer. As there is a scope for improvement and as a future implementation we can add a wireless webcam for capturing the images which will help in providing driver`s assistance. Keywords - Accident ,Automatic Detection, Micro electro Mechanical system , Remote Alarm Device, Vehicle
Controller for Network Interface Card on FPGA Suchita Kamble; N. N. Mhala
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (130.493 KB) | DOI: 10.11591/ijres.v1.i2.pp55-58

Abstract

The continuing advances in the performance of network servers make it essential for network interface cards (NICs) to provide more sophisticated services and data processing. Modern network interfaces provide fixed functionality and are optimized for sending and receiving large packets. Network interface cards allow the operating system to send and receive packets through the main memory to the network. The operating system stores and retrieves data from the main memory and communicates with the NIC over the local interconnect, usually a peripheral component interconnect bus (PCI). Most NICs have a PCI hardware interface to the host server, use a device driver to communicate with the operating system and use local receive and transmit storage buffers. NICs typically have a direct memory access (DMA) engine to transfer data between host memory and the network interface memory. In addition, NICs include a medium access control (MAC) unit to implement the link level protocol for the underlying network such as Ethernet, and use a signal processing hardware to implement the physical (PHY) layer defined in the network. To execute and synchronize the above operations NICs also contents controller whose architecture is customized for network data transfer. In this paper we present the architecture of application specific controller that can be used in NICs.

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