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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 5 Documents

Search results for , issue "Vol 1, No 3: November 2012" : 5 Documents clear

Design and Development of Texture Filtering Architecture for GPU Application Using Reconfigurable Computing Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. The designed texture filtering units are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU.

Queued-Stack Dataflow Processing Element for a Cognitive Sensor Platform Mark McDermott
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

This paper describes a Queued-Stack (QS) Dataflow Processing Element (DPE) that is used in a cognitive sensor platform. The queued-stack is used for buffering input data to the DPE and for storage of variables and results. The queuing mechanism and dataflow protocol provides the capability to compose multi-node computational systems where communication between elements is via non-blocking FIFO channels. System composition is achieved using synchronous dataflow tools such as SDF3 or Ptolemy. The dataflow-processing element is implemented using single cycle micro-coded engine where the ratio of datapath transistors to control logic is optimized for programmable energy-performance sensitive applications.

Digital Control of Static Var Compensator with Field Programmable Gate Array Ram Shankarrao Dhekekar; N. V. Srikanth
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

This paper is about real time simulation and implementation of FPGA Digital Control of Static VAR compensator for 750km lab model of artificial transmission line. In this paper, a new method of controlling SVC using Field Programmable Gate Array (FPGA) is suggested. FPGA controller is used to generate the firing pulses required to for Static Var Compensator. Pulses are synchronized with AC input; the delay of pulses determines the firing angle to driver circuit. The proposed control scheme has been realized using XILINX FPGA SPARTAN 2 XC2S200 and tested actual testing proves that these devices when installed, they keep the bus voltage same as reference voltage (sending-end voltage). The results are prominent and give a way for real-time implementation of the proposed control schemes. These control schemes are simulated for the real-time control along with real-time modeling and simulations.The results are prominent and give a way for real-time implementation

VHDL Implementation of H.264 Video Coding Standard Haresh A. Suthar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

This Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL.

Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi Mohammed Bilal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

In the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part. RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind of expandable, distributed large attendance logging system based on ARM Cortex M3 boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and HTML for man machine interface. This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol. The embedded board can act as a central CPU to communicate between web servers automatically.

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