International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
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<![CDATA[Hamming neural network application with FPGA device ]]>
<![CDATA[Liqaa Saadi Mezher]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp37-46
<![CDATA[The Hamming neural network is a kind of counterfeit neural system that substance of two kinds of layers (feed forward layers and repetitive layer). In this study, two pattern entries are utilization in the binary number. In the first layer, two nerves were utilization as the pure line work. In the subsequent layer, three nerves and a positive line work were utilization. The Hamming Neural system calculation was also implemented in three reproduction strategies (logical gate technique, programming program encryption strategy and momentary square chart technique). In this study in programming of VHDL and FPGA machine was utilization.]]>
<![CDATA[Ultra high speed full adder for biomedical applications ]]>
<![CDATA[Basavoju Harish]]>;
<![CDATA[M. S. S. Rukmini]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp25-31
<![CDATA[In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.]]>
<![CDATA[Characterization and hierarchical static timing analysis of mixed-signal design ]]>
<![CDATA[Sowmya K. B.]]>;
<![CDATA[Thanushree M.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp18-24
<![CDATA[As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.]]>
<![CDATA[Design and development of a parallelized algorithm for face recognition in mobile cloud environment ]]>
<![CDATA[K. N. Bhatt]]>;
<![CDATA[Sanket S Naik Dessai]]>;
<![CDATA[V. S. Yerragudi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp47-55
<![CDATA[Face recognition is the biometric application to recognise the identity. Face recognition application holds a set of images which are called databases stored by the user at cloud database. Cloud computing environment, database can be stored in the cloud environment to achieve huge data storage area. The problem with these data storages are that because of that huge size processing on this storage takes too much of compiling time. This paper aims to develop face recognition in mobile cloud environment by exploiting data or task parallelism in existing face recognition algorithms. To design and develop parallel PCA based face recognition algorithm. The parallel PCA face recognition algorithm has been deployed in the cloud server for performing PCA by request of user. It matches the image on the cloud server and gives response back to the user in the fewer amounts of time and with reduced latency. The developed Parallel PCA face recognition algorithm has minimized the overall response time for the face recognition algorithm. The performance of the developed system is tested and analysed on real face images. To analyse the developed system, a centralized and distributed based server methods are developed and comparison is being carried out. The conclusion drawn that the distributed server improves the efficiency as well as the computing power as compared with centralized server system. The comparison of centralized and distributed based servers is carried out by observing the time taken while varying the number of images in the training dataset.]]>
<![CDATA[Recurrence relation and DNA sequence: A state-of-art technique for secret sharing ]]>
<![CDATA[Anirban Bhowmik]]>;
<![CDATA[Sunil Karforma]]>;
<![CDATA[Joydeep Dey]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp65-76
<![CDATA[During the transmission over the Internet, protection of data and information is an important issue. Efficient cryptographic techniques are used for protection but everything depends on the encryption key and robustness of encryption algorithm. Threshold cryptography provides the development of reliable and strong encryption and key management machine which can reconstruct the message even in the case of destruction of some particular numbers of shares and at the opposite the data cannot be reconstructed unless an allowable set of shares are been gathered. The earlier techniques available in literature result in high computational complexity in the course of both sharing and reconstructing of message. Our method employs a brand new easy protecting technique based totally on unit matrix. The simple AND operation is used for percentage generation and reconstruction can be finished by way of easy ORing the stocks with threshold cost. We are proposing a sharing approach in conjunction with conventional cryptography technique for key control to make the key greater sturdy and for encryption we have used a session key the use of the idea of recurrence relation and DNA series Different types of experimental results confirm authenticity, confidentiality, integrity and acceptance of our technique.]]>
<![CDATA[Systematising troubleshooting of disputes in network ]]>
<![CDATA[Sowmya K. B.]]>;
<![CDATA[Thejaswini A.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp32-36
<![CDATA[With the growing network size, virtualization everywhere, it is getting more difficult to configure and manage the network devices. Software Defined Networking (SDN) is a way to address these problems. Application Centric Infrastructure (ACI) is the Cisco’s solution to SDN, with centralized automation and policy-driven application profiles. If there is any bug in the network or problem with the expected functionality of the network, ACI cases are opened in the Technical Assistance Centre (TAC) for troubleshooting the issue. Engineers currently troubleshoot ACI cases manually by using Command Line Interface (CLI) and trace for different events triggered by the policy pushes by logs generated at different stages of the ACI and from different servers responsible for this, which indeed is a very tedious, time consuming task and is prone to manual errors. This paper describes a way to automate the entire ACI troubleshooting process with the user-friendly GUI which can show the entire information needed for troubleshooting by extracting relevant information at every layer. By making use of FSM models the proposed solution can be extended to other areas which involve log analysis using CLI to extract relevant information and is not just limited to ACI.]]>
<![CDATA[Monolayer and bilayer graphene field effect transistor using Verilog-A ]]>
<![CDATA[Nayana G. H.]]>;
<![CDATA[Vimala P.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp56-64
<![CDATA[Monolayer and bilayer graphene field effect transistor modeling is presented in this paper. The transport model incorporated, works well for both drift diffusive and ballistic conditions. The validity of the model was checked for various device dimensions and bias voltages. Performance parameters affecting operation of graphene field effect transistor in various region of operation are optimized. Model was developed to verify transfer characteristics for monolayer and bilayer graphene field effect transistor. Results obtained prove the ambipolar property in Graphene. MATLAB is used for numerical modeling for systematic performance evaluation of parameters in graphene. The tool used to simulate the characteristics is cadence Verilog-A which describe analog component structure.]]>
<![CDATA[Smart metering system data analytics platform using multicore edge computing ]]>
<![CDATA[Juan C. Olivares-Rojas]]>;
<![CDATA[Enrique Reyes-Archundia]]>;
<![CDATA[José A. Gutiérrez-Gnecchi]]>;
<![CDATA[Ismael Molina-Moreno]]>;
<![CDATA[Adriana C. Téllez-Anguiano]]>;
<![CDATA[Jaime Cerda-Jacobo]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp11-17
<![CDATA[The smart grid revolution has only been possible, thanks to the development and proliferation of smart meters. The increasingly growing computing capabilities for Internet of Things devices have made it possible for data to be processed directly from the devices where it is produced; this has been called edge computing. Edge computing is allowing the smart grid to become increasingly intelligent to solve problems that make electricity consumption more efficient and environmentally friendly. This work presents the implementation of a smart metering system that allows data analytics using a multiprocessing architecture directly on the smart meter. The results show that the development of smart meters with data analytics capabilities at the edge is a reality today, and the use of multiprocessing permits the improvement of data processing.]]>
<![CDATA[A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST ]]>
<![CDATA[Kenta Shirane]]>;
<![CDATA[Takahiro Yamamoto]]>;
<![CDATA[Hiroyuki Tomiyama]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp1-10
<![CDATA[In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.]]>
