International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
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<![CDATA[Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins ]]>
<![CDATA[Ram Murti Rawat]]>;
<![CDATA[Vinod Kumar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp130-136
<![CDATA[This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.]]>
<![CDATA[FPGA implementation of Lempel-Ziv data compression ]]>
<![CDATA[Gody Mostafa]]>;
<![CDATA[Abdelhalim Zekry]]>;
<![CDATA[Hatem Zakaria]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp99-108
<![CDATA[When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.]]>
<![CDATA[Smart helmet using internet of things ]]>
<![CDATA[Mohamed A. Torad]]>;
<![CDATA[Mustafa Abdul Salam]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp90-98
<![CDATA[The rate of death relative to the size of the world’s population has remained constant, according to the world health organization (WHO). WHO targets to minimize the ratio of road death to the half by 2022. This paper discusses a way for accident detection and notification which can decrease this ratio. Piezoelectric sensors used inside a helmet to detect degree of trauma which interpret into electrical signal that used to determine if trauma is serious or not based on predetermined threshold. This trauma can be occuard due to any kind of accidents. So, this paper established a detection system to request instant help from emergency department and relatives by delivering them an SMS contains the latitude and longitude. In usual mode helmet can operate as tracking tool monitored by the relatives.]]>
<![CDATA[Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms ]]>
<![CDATA[Tirumale Ramesh]]>;
<![CDATA[Khalid Abed]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp77-89
<![CDATA[System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerable implementation economies with relatively small design cost for field programmable gate arrays (FPGAs) based embedded platforms. In this paper, we propose a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections. We generalize the system with b =min {n,m}/k number of interconnect buses in which where n is the number of processor cores, m is the number of memory-modules and k is the general bus reduction factor. We present four geometrical interconnect configurations and provide their characterization in terms of memory bandwidth, cost per bandwidth and bus fault tolerance for various system sizes. Our results show that these configurations provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.]]>
<![CDATA[Implementation of video surveillance system using embedded Blackfin processor ]]>
<![CDATA[Sanket Dessai]]>;
<![CDATA[Deepa Kannan]]>;
<![CDATA[Shiva Prasa Yadav]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp115-122
<![CDATA[The video surveillance is critical system to track the people at the various places and to track and monitor the nuciencess bound to be happened. On the other side several studies have proved and showed the hit and miss nature of human intervention to spot change in a surrounding environment which increasing the designer challenges for the development of video surveillance system with the help of embedded processor. The designer faces a greater challenge to apply the principle of embedded systems and develop the system smart features with low power and cost for the required applications of VSS. System requirement specification (SRS), Hardware design document (HDD), Software design document and test procedure has been arrived and developed to achieve VSS system. Blackfin processor has high end video engines and is more suitable for development of video surveillance system (VSS). The VSS is designed and developed using ADSP BF533 Ez-kit lite board. Peripheral like parallel peripheral interface (PPI) is used to interface between camera and processor. Also, it is used for interfacing processor and TV. The master-slave communication is established between two Blackfin processors through SPORT to transfer the captured frame from camera to display on TV. Power management is also implemented to save the power of the system.]]>
<![CDATA[An internet of things belief rule base smart system to predict earthquake ]]>
<![CDATA[Md. Mahashin Mia]]>;
<![CDATA[Abdullah Al Hasan]]>;
<![CDATA[Rahman Atiqur]]>;
<![CDATA[Rashed Mustafa]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp149-156
<![CDATA[An intelligent belief rule base (BRB) based system with internet of things (IoT) integration can evaluate earthquake prediction (EP). This ingenious and rational system can predict earthquake by aggregating changed animal behavior combined with environmental and chemical changes which are taken as real time inputs from sensors. The BRB expert system blends knowledge demonstration criterion like attribute weight, rule weight, belief degree. The intelligent BRB system with IoT predicts the probable occurrence of the earthquake in a region based on the sign and symptoms culled by the persistent sensors. The final result taken from Intelligent BRB system with IoT integration is compared with expert and fuzzy-based system. The projected method gives a better prediction than the up-to-date expert system and fuzzy system]]>
<![CDATA[Comparing reliabilities of centralized and distributed switching architectures for reconfigurable 2D arrays ]]>
<![CDATA[Behrooz Parham]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp123-129
<![CDATA[Whether used as main processing engines or as special-purpose adjuncts, processor arrays are capable of boosting performance for a variety of computation-intensive applications. For large processor arrays, needed to achieve the required performance level in the age of big data, processor malfunctions, resulting in loss of computational capabilities, form a primary concern. There is no shortage of alternative reconfiguration architectures and associated algorithms for building robust processor arrays. However, a commensurately extensive body of knowledge about the reliability modeling aspects of such arrays is lacking. We study differences between 2D arrays with centralized and distributed switching, pointing out the advantages of the latter in terms of reliability, regularity, modularity, and VLSI realizability. Notions of reliability inversion (modeling uncertainties that might lead us to choose a less-reliable system over one with higher reliability) and modelability (system property that makes the derivation of tight reliability bounds possible, thus making reliability inversion much less likely) follow as important byproducts of our study.]]>
<![CDATA[Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink ]]>
<![CDATA[Suneeta Suneeta]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp109-114
<![CDATA[Arbitrary numerals are utilized in a wide range of uses. Genuine arbitrary numeral generators are moderate and costly for some applications while pseudo arbitrary numeral generators (RNG) do the trick for most applications. This paper fundamentally concentrates around the co-simulation of the linear congruential generator (LCG) model utilizing the Xilinx System generator and checking on Matlab Simulink. The design is obtained from the LCG calculation offered by Lehmer. Word lengths decrease strategy has been utilized to streamline the circuit. Simulation has been done effectively. The effective N bit LCG is structured and tried by utilizing demonstrating in MatLab Simulink. The Co-simulation of the model is done by utilizing the Xilinx system generator. This paper conducts an exhaustive search for the best arbitrary numeral generator in a full period linear congruential generator (LCG) with the largest prime numbers.]]>
<![CDATA[Processor performance metrics analysis and implementation for MIPS using an open source OS ]]>
<![CDATA[Varuna Eswer]]>;
<![CDATA[Sanket Dessai]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp137-148
<![CDATA[Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varying load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction execution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twentyseven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analyzing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterization and kernel profiling.]]>
