Garuda - Garba Rujukan Digital

Article Per Year (5 Year)

All

International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
Website

Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 7 Documents

Search results for , issue "Vol 8, No 1: March 2019" : 7 Documents clear

Performance evaluation of embedded ethernet and Controller Area Network (CAN) in real time control communication system Ching Chia Leong; Mohamad Khairi Ishak
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Real-time communication is important in control network. In real-time communication, message need to be delivered from source to destination within specification. Embedded Ethernet and Controller Area Network (CAN) protocol can be used in control network to achieve hard real-time communication. For embedded Ethernet protocol, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) is the media access control (MAC) used to control data transmission between nodes in network. Back-off algorithm in CSMA/CD is used to handle packet collisions and retransmission. For CAN protocol, it is communication protocol developed mainly for automotive application. It has priority arbitration to handle collisions and retransmission. In this project, embedded Ethernet network models and CAN network models are developed and simulated in MATLAB Simulink software. Several back-off algorithms, which are Binary Exponential Backoff (BEB), Linear Back-off Algorithm, Exponential-Linear back-off Algorithm and Logarithm Back-off Algorithm are proposed and implemented into Embedded Ethernet network model to evaluate the performance. Both embedded Ethernet and CAN network models are extended to 3 nodes, 10 nodes, and 15 nodes to evaluate performance at different network condition. The performance criteria evaluated and discussed are average delay and jitter of packets. The results show that in network with high number of nodes, Linear Back-off Algorithm and Exponential-Linear back-off Algorithm shows improvement in packets delay and jitter. For CAN network, the packet jitter is relatively low.

Secured smart ATM transaction C. R. Balamurugan; K. Ramash kumar; A. Thirumalai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

The objective of this paper is to reduce the service tax during mobile transactions. To improve the security and to make the process easy and less time consuming this process is rendered with the help of GSM (Global System for Mobile communication), finger print sensors, PIC16F877A microcontroller and aadhaar number.

Design of a 60 GHz power amplifier in a 45nm CMOS Rashmi S. B.; Siva S. Yellampalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

This Paper presents a design and implementation of class-AB power amplifier which works at 60GHz unlicensed frequency band. This power amplifier uses a MOSFET from gpdk45 technology library. The design simulation is done by cadence Analog Design Environment. This proposed power amplifier yields a power added efficiency of 23.45% and a power gain S21 of 10dB at 60GHz. The output impedance of proposed power amplifier is needs to be matched with 73Ω antenna impedance. The S22 output matching of the simulated power amplifier is -18dB at 60GHz. The input side is matched to arbitrary impedance of 50Ω the resulting S11 of simulated result is noted to be -15dB at 60GHz. The proposed circuit has a noise figure of 3.85dB. The proposed circuit has a Pout-1dB of 8.5dBm. the designed class AB power amplifier is an important component in 60GHz transceiver. The layout of the associated circuit is drawn with the total size of 0.107um2.

FPGA implementation of new LM-SPIHT colored image compression with reduced complexity and low memory requirement compatible for 5G Yasmine M. Tabra; Bayan Mahdi Sabbar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

The revolution in 5G mobile systems require changes to how image is handled. These changes are represented by the required processing time, the amount of space for uploading and downloading. In this paper, a development on WT (Wavelet Transform) along with LM-SPIHT (Listless-Modified Set Partitioning in Hierarchical tree) coding and with additional level of Runlength encoding for image compression has been proposed. The new implementation reduces the amount of data needed to be stored in several stages, also the amount of time required for processing. The compression has been implemented using VHDL (Very High Descriptive Language) on netFPGA-1G-CLM Kintex-7 board. The new implementation results show a reduction in the complexity as processing time.

Design of active inductor-based butterworth and chebyshev microwave bandpass filters in standard 0.18µm-CMOS technology Jarjar Mariem; Pr. EL Quazzani Nabih
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

In this paper we propose a synthesis of microwave active filters having Butterworth and Chebyshev responses in the frequency range 1GHz-2GHz. The filter fundamental block, used to build an active inductor, consists of CMOS-based Operational Transconductance Amplifier (OTA) circuits. These amplifiers are made out of simple current mirror using MOS transistors. The simulation procedure has been carried out through PSPICE software showing good performances regarding scattering parameters in terms insertion losses, of out-of-band rejection and phase.

Design and software characterization of finFET based full adders Raju Hajare; C. Lakshminarayana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

Verilog based efficient convolution encoder and viterbi decoder Md. Abdul Rawoof; Umasankar Ch.; D. Naresh Kumar; D. Khalandar Basha; N. Madhur
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

In the today’s digital communication Systems, transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

Page 1 of 1 | Total Record : 7

Filter by Year

2019 2019

Filter By Issues

All Issue Vol 14, No 2: July 2025 Vol 14, No 1: March 2025 Vol 13, No 3: November 2024 Vol 13, No 2: July 2024 Vol 13, No 1: March 2024 Vol 12, No 3: November 2023 Vol 12, No 2: July 2023 Vol 12, No 1: March 2023 Vol 11, No 2: July 2022 Vol 11, No 1: March 2022 Vol 10, No 3: November 2021 Vol 10, No 2: July 2021 Vol 10, No 1: March 2021 Vol 9, No 3: November 2020 Vol 9, No 2: July 2020 Vol 9, No 1: March 2020 Vol 8, No 3: November 2019 Vol 8, No 2: July 2019 Vol 8, No 1: March 2019 Vol 7, No 3: November 2018 Vol 7, No 2: July 2018 Vol 7, No 1: March 2018 Vol 6, No 3: November 2017 Vol 6, No 2: July 2017 Vol 6, No 1: March 2017 Vol 5, No 3: November 2016 Vol 5, No 2: July 2016 Vol 5, No 1: March 2016 Vol 4, No 3: November 2015 Vol 4, No 2: July 2015 Vol 4, No 1: March 2015 Vol 3, No 3: November 2014 Vol 3, No 2: July 2014 Vol 3, No 1: March 2014 Vol 2, No 3: November 2013 Vol 2, No 2: July 2013 Vol 2, No 1: March 2013 Vol 1, No 3: November 2012 Vol 1, No 2: July 2012 Vol 1, No 1: March 2012 More Issue

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name -

Contact Email -

Phone -

Journal Mail Official -

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA