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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

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Articles 8 Documents

Search results for , issue "Vol 8, No 2: July 2019" : 8 Documents clear

Performance optimization of task intensive real time applications on multicore ECUs - a hybrid scheduler Geetishree Mishra; Rajeshwari Hegde
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

In the current approach of Automotive electronic system design, the multicore processors have prevailed to achieve high computing performance at low thermal dissipation. Multicore processors offer functional parallelism that helps in meeting the safety critical requirements of vehicles. The number of ECUs in high-end cars could be reduced by conglomerating more functions into a multicore ECU. AUTOSAR stack has been designed to support the applications developed for multicore ECUs. The real challenges lie in adapting new design methods while developing sophisticated applications with multicore constraints. It is imperative to utilize the most of multicore computational capability towards enhancing the overall performance of ECUs. In this context the scheduling of the real time multitasking software components by the operating system is one of the key issues to be addressed. In this paper, the state of the art scheduling algorithm is reviewed and its merits and limitations are identified. A hybrid scheduler has been proposed, tested and compared with the state of the art algorithm that offers better performance in terms of CPU utilization, average response time and deadline missing rate both in normal and high load conditions.

Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology S.Tamil Selvan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.

Integration testing based on indirect interaction for embedded system Muhammad Iqbal Hossain; Woo Jin Lee
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

Embedded systems comprise several modules that exchange data by interacting among themselves. Exchanging wrong resource data among modules may lead to execution errors or anomalies. Interacting resources produce dependencies between two modules where any change of resources by one module affects the functionality of another module. Several investigations of the embedded system such as aerospace or automobile system show interaction faults between modules are one of the major cause of critical software failures. Therefore, interaction testing is an essential phase to reduce the interaction faults and minimize the risk. The direct and indirect interaction between modules generates interaction faults where indirect interaction is made underneath the interface in which data dependence relationship with resources may cause a different outcome. We investigate errors based on the indirect interaction between modules and introduce a new test criterion for finding errors detectable by existing approaches in unit level but not in integration level. In this paper, we propose a noble approach to generate an interaction model using indirect interaction pattern and design test criteria based on different interaction errors to generate test cases. Finally, we use fault injection and data flow coverage techniques to evaluate the feasibility and effectiveness of our approach

Neuronal logic gates realization using CSD algorithm Lakshmi kiran Mukkara; K.Venkata Ramanaiah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial neural networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.

Low power and high performance FFT with different radices Md. Zakir Hussain; Kazi Nikhat Parvin
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.

Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor R. Palanisamy; K. Vijayakumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

Notice of Retraction: Implement embedded controller using FPGA chip Haresh Pandya; Mahesh Rangapariya; Jitendra Rajput
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

This article has been retracted by the publisher.Notes: Notice of Retraction: After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles. We hereby retract the content of this paper. Reasonable effort should be made to remove references to this paper. The presenting author of this paper has the option to appeal this decision by contacting info@iaesjournal.com.------------------------------------The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.

Design and implement of high gain and low noise neural amplifier using compensation techniques N. Manikandan; S. Muruganand; K. Karuppasamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

Electroencephalography is refer to record the electrical signal with respect to brain activity and its reliable EEG information, using this to diagnosis disorder and tumors. However the signal is very difficult to capture and processing due to so many parameter. Mainly this signal is very low range that from 0.1 to 100μv in and its bandwidth range from 1Hz to 100 Hz. So the signal has amplified by using linear and accurate digital program amplifier(PGA).This amplifier has been designed by using First stage amplifier with gain of 120dB with low output noise. The PGA is consists of OPAMPs the PGA change from 10 dB to 120dB.Inorde to optimized the linear and gain accuracy a new structure resister array is proposed high gain PGA. Hence the simulated result has shown it is promising to exhibit an amplifier with high performance biomedical application.

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