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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 63 Documents
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Search results for , issue "Vol 14, No 2: May 2019" : 63 Documents clear
Design and analysis of dedicated real-time clock for customized microcontroller unit M.N. A.M. Alias; S. N. Mohyar; M. N. Isa; A. Harun; A. B. Jambek; S.A. Z. Murad
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp796-801

Abstract

In this paper, a Real Time Clock (RTC) system for a dedicated microcontroller is proposed to provide the customized microcontroller its own time and date system. The RTC is developed using Verilog Hardware Description Language (HDL) and simulated using Synopsys software. This RTC is developed with standard Advance Peripheral Bus (APB) to be interfacing with the microcontroller through Advanced Microcontroller Bus Architecture (AMBA). This RTC will be used as an on-chip RTC in the microcontroller system to provide precise time and date which can be used for various applications. The basic architecture of RTC, APB standard for interfacing the RTC with AMBA bus, and the result in term of RTL, waveform, and layout will be discussed in this documentation. For this research, the part covered is on the logic part of the RTC that is bus interface, register, frequency divider and counter.
An approach to building energy clusters using particle swarm optimization algorithm for allocating the tasks in computational grid Rashedul Islam; Md Nasim Akhtar; Badlishah R Ahmad; Utpal Kanti Das; Mostafijur Rahman; Zahereel Ishwar Abdul Khalib
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp826-833

Abstract

The proper mapping in case of allocation of available tasks among particles is a challenging job to accomplish. It requires proper procedural approach and effectual algorithm or strategy. The deterministic polynomial time for task allocation problem is relative. The existence of proper and exact approach for allocation problem is void. However, for the survival of the grid and executing the assigned tasks, the reserved tasks need to be allocated equally among the particles of the grid space. At the same time, the applied model for task allocation must not consume unnecessary time and memory. We applied Particle Swarm Optimization (PSO) for allocating the task. Additionally, the particles will be divided into three clusters based on their energy level. Each cluster will have its own cluster header. Cluster headers will be used to search the task into space. In a single cluster, particles member will be of same energy level status such as full energy, half energy, and no energy level. As a result, the system will use the limited time for searching task for the remaining tasks in it if a particular task requires allocating half task to a particle.
A coarse-to-fine copy-move image forgery detection method based on discrete cosine transform Mas Elyna Azol; Nur Hidayah Ramli; Y.S. Lee Lee; Siti Azura Abuzar
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp843-851

Abstract

Copy-move forgery is a type of image forgery where one part of an image is copied and pasted in other regions of the same image, and it is one of the most common image forgeries to conceal some information in the original image. Discrete Cosine Transform (DCT) is one of the detection techniques which the detection rate relies intensely on the size of block used. Small block size is known for its ability to detect fine cloned objects, but the drawback is it produces too many false positive and requires high execution time. In this research, a method to overcome the weaknesses of using small block size by applying the coarse-to-fine approach with the two-tier process is proposed. The proposed method is evaluated on fifteen forged images on the CoMoFoD dataset. The results demonstrated that the proposed method is able to achieve high precision and recall rate of over 90% as well as improves the computation time by reducing the overall duration of forgery detection up to 73% compared to the traditional DCT method using small block size.  Therefore, these findings validate that the proposed method offers a trade-off between accuracy and runtime.
Analysis and design of directive antenna using frequency selective surface superstrate Siti Rohani Tajuddin; S. N. Azemi; P. J. Soh; C.B.M. Rashidi; A Abdullah Al-Hadi
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp529-536

Abstract

The design of directive antenna using Frequency Selective Surface (FSS) superstrate is proposed in this project. The suitable design FSS as superstrate layer is very important to enhance the high directivity and narrow bandwidth on the antenna. By using the FSS layer to design the superstrate layer, there are able to determine the reflection coefficient accordingly to the desired frequency.
Characterization of cracking in pavement distress using image processing techniques and k-Nearest neighbour A. Ibrahim; M.K. Osman; N.A.M. Yusof; K.A. Ahmad; N.H. Harun; R.A.A. Raof
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp810-818

Abstract

This study presents characterization of cracking in pavement distress using image processing techniques and k-nearest neighbour (kNN) classifier. The proposed semi-automated detection system for characterization on pavement distress anticipated to minimize the human supervision from traditional surveys and reduces cost of maintenance of pavement distress. The system consists of 4 stages which are image acquisition, image processing, feature extraction and classification. Firstly, a tool for image acquisition, consisting of digital camera, camera holder and tripod, is developed to capture images of pavement distress. Secondly, image processing techniques such as image thresholding, median filter, image erosion and image filling are applied. Thirdly, two features that represent the length of pavement cracking in x and y coordinate system namely delta_x and delta_y are computed. Finally, the computed features is fed to a kNN classifier to build its committee and further used to classify the pavement cracking into two types; transverse and longitudinal cracking. The performance of kNN classifier in classifying the type of pavement cracking is also compared with a modified version of kNN called fuzzy kNN classifier. Based on the results from images analysis, the semi-automated image processing system is able to consistently characterize the crack pattern with accuracy up to 90%. The comparison of analysed data with field data shows good agreement in the pavement distress characterization. Thus the encouraging results of semi-automated image analysis system will be useful for developing a more efficient road maintenance process.
A data mining process using classification techniques for employability prediction Saouabi Mohamed; Abdellah Ezzati
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp1025-1029

Abstract

The use of the data mining has become wider today; it can be applied in several fields like marketing, customer relationship management, medicine, engineering, etc. It can be used also in employability, the use of data mining in this field will give opportunities and solution for decision makers in this field in order to improve the employability and propose solutions. In this paper, we propose a data mining process for employability data using classification techniques, presenting in details all the phases in the process and what should be done in every phase. We used Rapid Miner Studio Educational Version 8.1.000, using an employability dataset.
An architecture of 5G based on SDN NV wireless network Abeer .A. Z. Ibrahim; Fazirulhisyam Hashim
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp725-734

Abstract

The unexpected increase demand growth of broadband traffic, rapid advancement in networking and internet technology led to the growth in Internet-connected devices to sensor networks, and machine type communication devices. These increases bring more challenges in network capacity and connectivity. The use of the new 5G technology continues to address these challenges by providing high data rates, low latency, and more mobility with highly and densified HetNe deploment. This densified network brings new challenges to service provisioning in future networks based on the recent network paradigm innovations, Network Virtualization and Software Defined Networking to cope with massive broadband connectivity and enhancement of capacity, flexibility, and scalability. This study sets out to present the key features and requirements for 5G HetNet, SDN and NFV.  The results of this study generally justify the challenges and how to integrate them into future wireless networks through a proposed 5G-based SDN-NV wireless network architecture to enable best network performance and resource management.
Optimum reactive power to improve power factor in industry using genetic algortihm Ahmad Yani; Junaidi Junaidi; M. Irwanto; A. H. Haziah
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp751-757

Abstract

Capacitor bank is a collection of power tools in the form of a capacitor that serves as a tool that can reduce or improve reactive power into the power grid. The load on the electricity network in general is an inductive load. If the average power factor (cos ϴ) is less than 0.85, the State Electricity Company will provide the reactive power in KVAR fines usage charges on customers. An effort should be done to reduce the reactive power. An installation of bank capacitor is suitable to be implemented in an industry AC loads. It will reduce the reactive power and improve the power factor. In the case of 380 V, 50 Hz, 500 kW AC loads are improved the power factor from 0.7 to 0.93 using genetic algorithm, thus the AC loads current and reactive power will be decreased. It is suitable that the AC loads current is inversely proportional to the power factor, and the reactive power is proportional to the AC loads current.
Corrupted packets discarding mechanism to alleviate congestion in wireless body area network Wan Aida Nadia Wan Abdullah; Naimah Yaakob; R. Badlishah Ahmad; Mohamed Elshaikh Elobaid; Siti Asilah Yah
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp581-587

Abstract

Generation of high traffic from continuous sensing and collection of medical data from various biosensors on multiple body is most likely to occur in the Wireless Body Area Network (WBAN). This could be a factor to the congestion in the network. Occurrence of congestion would collapse the performances in the WBAN network in terms of increment in delay, high packets loss, reduction in throughput and packet deliver ratio (PDR). The crucial concerns in WBAN are prevention from the loss of critical data and longer delay in the network as they could result to late delivery of medical treatment and possibility of the increase in mortality. Therefore, this study proposes a mechanism to alleviate the congestion from happening in the first place through discarding the corrupted packets before the beginning of data transmission to the base station. Extensive simulations are done in OMNeT+ to analyze the performance of the proposed mechanism by varying traffic from low to high under different number of nodes and constant Bit Error Rate (BER) and packet size. From the finding, it can be concluded that the proposed mechanism shows better performances in terms of low delay and packet loss as well as high throughput and PDR compared to typical WBAN.
Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques Salahuddin Savugathali; Muslim Mustapa; Mohammed Sharazel Razali; Fazrul Faiz Zakaria
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp628-636

Abstract

A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.

Page 4 of 7 | Total Record : 63

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