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Indonesian Journal of Electrical Engineering and Informatics (IJEEI)

IJEEI
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Published by IAES Indonesia Section and Partners

ISSN : 20893272 EISSN : - DOI : -

Core Subject : Science, Engineering,

Computer Science & IT Electrical & Electronics Engineering

Indonesian Journal of Electrical Engineering and Informatics (IJEEI) is a peer reviewed International Journal in English published four issues per year (March, June, September and December). The aim of Indonesian Journal of Electrical Engineering and Informatics (IJEEI) is to publish high-quality articles dedicated to all aspects of the latest outstanding developments in the field of electrical engineering. Its scope encompasses the engineering of Telecommunication and Information Technology, Applied Computing & Computer, Instrumentation & Control, Electrical (Power), Electronics, and Informatics.

Arjuna Subject : -

Articles 783 Documents

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Self-adaptive fuzzy-PID controller for AGC study in deregulated Power System Subhadra Sahoo; Narendra Kumar Jena; Geetanjali Dei; Binod Kumar Sahu
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 4: December 2019
Publisher : IAES Indonesian Section

The aim of this paper elucidates the AGC issues in a large scale interconnected power system incorporating HVDC link under the deregulated environment. The performance of the system is degraded under the influence of abrupt load change, and parameter variation. To perceive a reliable and quality power supply, secondary robust controllers are essential. A novel self-adaptive Fuzzy-PID controller is proposed to ameliorate the dynamic performance of both the conventional PID and Fuzzy-PID controller, employed in the restructured power system. In self-adaptive Fuzzy-PID controller unlike the Fuzzy-PID controller, the output scaling factors are tuned dynamically while the controller is functioning. These three controllers are designed by enumerating different gains and scaling factors, applying a budding nature-inspired algorithm known as Wild Goat Algorithm (WGA). The superior dynamic performance of frequency and tie-line power deviation under self-adaptive Fuzzy-PID controller in comparison to its' counterparts is investigated by dispatching the scheduled and unscheduled power under different contracts such as poolco based transaction, bilateral transaction and contract violation based transaction through different tie-lines. The dynamic response under parameter variation and random load perturbation confers the robustness of the proposed controller.

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology N Mathan; S Jayashri; Nurul Ezaila Alias; Michael Loong Peng Tan
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 4: December 2019
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v7i4.1459

In VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved power consumption by 76.47% ,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier.

Application of modified least squares method for order reduction of commensurate higher order fractional systems Kalyana Kiran Kumar; Chongala Prasad; S Ramanjaneyulu Korada; B. Srinivasa Rao
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

The paper related to the reduction and investigation of family of commensurate fractional order systems. The fractional order system is first transformed to integer order and then a hybrid method is applied as a model reduction scheme. In this scheme the reduced denominator is acquired by least square method and the numerator is achieved by time moment matching. This formulated reduced integer model is reconverted to reduced fractional model. Three examples are conferred to authenticate and emphasize the efficacy of the proposed approach. The proposed method is verified by MATLAB simulation, and shows better performance in the estimation process.

A Novel Design and Implementation of FBMC Transceiver for Low Power Applications Mohamed Saber
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

The complex structure of the Filter Bank Multicarrier (FBMC) communication system is the main drawback affecting the performance of the system and causes a high-power consumption. The complexity arises from using a polyphase filter bank, which consists of fast Fourier Transform/ Inverse Fast Fourier Transform (FFT/IFFT) processors and a filter bank of Finite Impulse Response (FIR) filters. This paper presents the analysis and the implementation of a new design model for FBMC transceiver in which the polyphase filter is removed completely in both transmitter and receiver and uses instead of it, a multi-level cascaded structure of FIR subfilters. The coefficients of each subfilter selected using an optimization algorithm to minimize the amplitude of sidelobes compared to the amplitude of the main lobe in the frequency response of the subfilter. The proposed design reduces the number of multiplications compared to the conventional design by 65%. The field-programmable gate array (FPGA) implementation results indicate that the proposed architecture saves 24% of resources of the FPGA board, works faster, and saves 27% of power consumption compared to conventional FBMC transceiver.

Double-talk robust acoustic echo canceller based on CNN filter Haengwoo Lee
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

Conventional acoustic echo cancellation works by using an adaptive algorithm to identify the impulse response of the echo path. In this paper, we use the CNN neural network filter to remove the echo signal from the microphone input signal, so that only the speech signal is transmitted to the far-end. Using the neural network filter, weights are well converged by the general speech signal. Especially it shows the ability to perform stable operation without divergence even in the double-talk state, in which both parties speak simultaneously. As a result of simulation, this system showed superior performance and stable operation compared to the echo canceller of the adaptive filter structure.

Performance Analyses of Graph Heuristics and Selected Trajectory Metaheuristics on Examination Timetable Problem Ashis Kumar Mandal; M.N.M. Kahar
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

Examination timetabling problem is hard to solve due to its NP-hard nature, with a large number of constraints having to be accommodated. To deal with the problem effectually, frequently heuristics are used for constructing feasible examination timetable while meta-heuristics are applied for improving the solution quality. This paper presents the performances of graph heuristics and major trajectory metaheuristics or S-metaheuristics for addressing both capacitated and un-capacitated examination timetabling problem. For constructing the feasible solution, six graph heuristics are used. They are largest degree (LD), largest weighted degree (LWD), largest enrolment degree (LE), and three hybrid heuristic with saturation degree (SD) such as SD-LD, SD-LE, and SD-LWD. Five trajectory algorithms comprising of tabu search (TS), simulated annealing (SA), late acceptance hill climbing (LAHC), great deluge algorithm (GDA), and variable neighborhood search (VNS) are employed for improving the solution quality. Experiments have been tested on several instances of un-capacitated and capacitated benchmark datasets, which are Toronto and ITC2007 dataset respectively. Experimental results indicate that, in terms of construction of solution of datasets, hybridizing of SD produces the best initial solutions. The study also reveals that, during improvement, GDA, SA, and LAHC can produce better quality solutions compared to TS and VNS for solving both benchmark examination timetabling datasets.

Wi-Fi For Indoor Device Free Passive Localization (DfPL): An Overview Rajeshkumar Gunasagaran; Latifah Munirah Kamarudin; Ammar Zakaria
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

The world is moving towards an interconnected and intercommunicable network of animate and inanimate objects with the emergence of Internet of Things (IoT) concept which is expected to have 50 billion connected devices by 2020. The wireless communication enabled devices play a major role in the realization of IoT. In Malaysia, home and business Internet Service Providers (ISP) bundle Wi-Fi modems working in 2.4 GHz Industrial, Scientific and Medical (ISM) radio band with their internet services. This makes Wi-Fi the most eligible protocol to serve as a local as well as internet data link for the IoT devices. Besides serving as a data link, human entity presence and location information in a multipath rich indoor environment can be harvested by monitoring and processing the changes in the Wi-Fi Radio Frequency (RF) signals. This paper comprehensively discusses the initiation and evolution of Wi-Fi based Indoor Device free Passive Localization (DfPL) since the concept was first introduced by Youssef et al. in 2007. Alongside the overview, future directions of DfPL in line with ongoing evolution of Wi-Fi based IoT devices are briefly discussed in this paper.

FOPID Controlled Shunt Active Filter in IEEE Thirty Bus System with Improved Dynamic Time Response Sundaramoorthy Dhandayuthapani; K Anisha
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

This paper aims on improving the dynamic time response of a Wind Energy Conversion System (WECS) connected to IEEE Thirty Bus System(TBS) using Permanent Magnet Synchronous Generator (PMSG) in closed loop controlled Active Power Filter with FOPID. The simulation results are presented to find the effect of shunt active filter using FOPID controller. Open Loop Thirty Bus System (OLTBS) with change in load is simulated. The simulation results with PI and FOPID Controller based SAF are compared and the corresponding time-domain parameters are presented. The results indicate that FOPID Controller system has better response than PI controlled system.

Reducing Beat Frequency Oscillation in a Two-phase Sliding Mode-controlled Voltage Regulator Module Jessica C Magsino; Elmer Ramilo Magsino
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

During static and dynamic loading conditions, voltage regulator modules (VRMs) are expected to provide regulated voltage with minimal ripple even at high current requirement. Compared to regular power supplies, VRMs repetitively experience high-frequency loading conditions that is greatly dependent on the software running in the processor utilizing them. In the scenario that when the transient load frequency is near the VRM’s switching frequency, high-magnitude and low-frequency oscillations are observed at the phase currents. This phenomenon is called the beat frequency oscillation. In this study, the sliding mode control principle is employed to both the voltage and current share loops of the VRM to reduce the phase currents’ beat frequency oscillations. A fixed frequency sliding mode controller is derived and extensively evaluated using the PSIM simulator. Our results show that while maintaining equal load sharing among VRMs at less than 5% sharing error and various types of loading conditions, the sliding mode controller can reduce the beat frequency oscillation phenomenon to 20 kHz at maximum with reduced peak current values. The output voltage is also regulated within the desired ±1.65% band.

Automated Detection of Retinal Hemorrhage based on Supervised Classifiers K.A Sreeja; S.S Kumar
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 1: March 2020
Publisher : IAES Indonesian Section

Supervised machine learning algorithm based retinal hemorrhage detection and classification is presented. For developing an automated diabetic retinopathy screening system, efficient detection of retinal hemorrhage is important. Splat, which is a high level entity in image segmentation is used to mark out hemorrhage in the pre-processed fundus image. Here, color images of retina are portioned into different segments (splats) covereing the whole image. With the help of splat level and GLCM features extracted from the splats, three classifiers are trained and tested using the relevant features. The ground-truth is established with the help of a retinal expert and using dataset and clinical images the validation was done. The output obtained using the three classifiers had more than 96 % sensitivity and accuracy.

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