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Optimal thermo-QoS-aware routing protocol for WBAN communication Bedi, Pardeep; Das, Sanjoy; Goyal, S. B.; Kumar, Manoj; Gupta, Sunil
Indonesian Journal of Electrical Engineering and Computer Science Vol 41, No 1: January 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v41.i1.pp270-282

Abstract

Wireless body area network (WBAN) has emerged as a promising solution to address problems such as population aging, a lack of medical facilities, and different chronic ailments. WBANs have real-time applications, and there is an increasing demand for them. However, due to changing network structure, power supply limitations, and constrained computing capacity, energy constraints, it is difficult task to achieve quality of service (QoS). To mitigate these limitations, the paper proposed an optimal thermo-QoS aware routing protocol (OTQRP) for WBAN communication. The result was investigated in terms of temperature rise, energy consumption and delay. The paper shows better energy efficiency with respect to existing works. Finally, OTQRP feature comparison is also presented with recent research in terms of features such as complexity, latency, and energy economy and observed that OTQRP shows best performance as compared to others.
FPGA implementation of a coprocessor architecture for random data generation and encryption Kumar, Manoj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp21-30

Abstract

Coprocessors are designed to perform some specific tasks to enhance system performance and speed. Information security is the main focus in internet of thing (IoT), cryptography, and cybersecurity applications. In this work, a coprocessor architecture is designed to generate 4-bits of random data and perform encryption. Coprocessor architecture uses true random number generator (TRNG) and pseudo-random number generator (PRNG) architectures to generate random data. Modified linear feedback shift register (LFSR)-based PRNG and modified transition effect ring oscillator (TERO) and ring oscillator-based TRNG architectures are designed and implemented for performing encryption. A serial-in-parallel-out (SIPO) shift register circuit is used to generate 4-bit random data. A 15-bit instruction word is assigned to coprocessor architecture to perform its task. The coprocessor architecture is designed using VHSIC Hardware Description Language (VHDL) and implemented on an Artix-7 field programmable gate array (FPGA). All simulation and synthesis results of the proposed coprocessor architecture are obtained by the Xilinx Vivado 2015.2 tool. Coprocessor architecture efficiency (throughput (Mbps)/LUTs) is 2.31, and it operates at a 100 MHz clock.