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All Journal Syntax Idea Eduvest - Journal of Universal Studies
Arachman, Setyo Arief
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Aerospace Engineering Agriculture, Biological Sciences & Forestry Automotive Engineering Chemical Engineering, Chemistry & Bioengineering Computer Science & IT Health Professions Neuroscience Social Sciences

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Analisis Knowledge Management Maturity Level Dengan Metode Siemens Maturity Level (Studi Kasus : STIMIKESQ) Widiatuti, Mariska Aprisciliana; Arachman, Setyo Arief; Broto, Agustinus
Syntax Idea Vol 1 No 7 (2019): Syntax Idea
Publisher : Ridwan Institute

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Abstract

Penelitian ini bertujuan untuk mengukur tingkat kematangan (maturity level) knowledge management di program studi Sistem Informasi STIMIK ESQ dan pengaruh tingkat kematangan (maturity level) terhadap penciptaan pengetahuan baru di program studi Sistem Informasi STIMIK ESQ. Penelitian ini menggunakan pendekatan Siemens Maturity Model dalam pengukurannya. Dalam hal ini dilakukan penelitian terhadap 21 informan yaitu 5 informan dosen dan 16 informan mahasiswa dengan 2 informan yang tidak valid. Penelitian ini menggunakan metode penelitian kualitatif yaitu observasi, wawancara, dan dokumentasi. Sebanyak 60% matakuliah melakukan pembelajaran melalui practical and case study, hanya 80% SAP yang diajarkan, mahasiswa yang mereview materi perkuliahan sebanyak 13,3% dan sebanyak 73,3% baru mereview materi menjelang assessment atau ujian akhir sedangkan 13,3% mahasiswa yang mencari materi perkuliahan selain yang diajarkan. Hasil dari penelitian ini menunjukkan bahwa tingkat kematangan knowledge management di STIMIK ESQ berada di level repeated sehingga dalam hal ini belum terciptanya pengetahuan di STIMIK ESQ tersebut. Namun terdapat penciptaan pengetahuan di matakuliah tecnopreneur yang didapat melalui proses experience learning dan exploring.
The Role of Cache Memory In Enhancing Microprocessor Performance in PT. Srikandi Sinergi Sakti Hendarin, Hendarin; Riwurohi, Jan Everhard; Arachman, Setyo Arief
Eduvest - Journal of Universal Studies Vol. 4 No. 12 (2024): Journal Eduvest - Journal of Universal Studies
Publisher : Green Publisher Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59188/eduvest.v4i12.43139

Abstract

Cache memory in microprocessors has an important role in improving computer system performance by reducing data access time. This research aims to test the hypothesis that increasing the size and level of cache memory can significantly improve microprocessor performance. The research methodology involves a literature study on the concept of cache memory and experimental simulations using computer architecture simulators, such as Gem5, to model scenarios with varying cache sizes and levels. In these simulations, performance parameters such as memory access latency, throughput, and Instructions Per Cycle (IPC) were measured and analyzed. The results show that increasing cache size and level generally contributes towards improving microprocessor performance by reducing data access time. Further statistical analysis supports the hypothesis that there is a positive correlation between cache size and level and system efficiency. These findings provide useful insights in future microprocessor architecture design and memory system optimization.
Co-Authors Broto, Agustinus Hendarin, Hendarin Mariska Aprisciliana Widiatuti, Mariska Aprisciliana Ruwirohi, Jan Everhard