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All Journal IAES International Journal of Robotics and Automation (IJRA) International Journal of Informatics and Communication Technology (IJ-ICT) International Journal of Supply Chain Management Computer Science and Information Technologies
Kumar, Adesh
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Automotive Engineering Computer Science & IT Decision Sciences, Operations Research & Management Electrical & Electronics Engineering Engineering Environmental Science Industrial & Manufacturing Engineering Transportation

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Demand Planning: Riding Disruptive Wave of AI and Accelerated Computing Khastgir, Antara; Kumar, Adesh
International Journal of Supply Chain Management Vol 13, No 2 (2024): International Journal of Supply Chain Management (IJSCM)
Publisher : ExcelingTech

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59160/ijscm.v13i2.6236

Abstract

Traditional demand planning methods often struggle to keep pace with the complexity, volatility, and vast datasets inherent in modern supply chains. Artificial intelligence (AI) offers a transformative solution, revolutionizing demand planning with its ability to analyze vast amount of data, identify complex patterns, and generate highly accurate forecasts. This paper explores the latest advancements in AI for demand planning, encompassing machine learning, deep learning, and natural language processing (NLP). The focus is on how these techniques enhance demand sensing capabilities, incorporating real-time market signals, external data sources, and unstructured text information. Furthermore, the potential of AI to optimize inventory management, enable scenario planning, and increase supply chain resilience in response to unexpected disruptions are examined. The paper also addresses practical challenges in implementing AI-powered demand planning solutions, and outlines areas for future research. Most importantly, the paper provides the robust methologies to integrate the emerging AI developments in demand planning process.
Design and implementation of deep neural network hardware chip and its performance analysis Pant, Aruna; Kumar, Adesh
IAES International Journal of Robotics and Automation (IJRA) Vol 13, No 4: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v13i4.pp485-494

Abstract

The artificial neural network (ANN) with a single layer has a limited capacity to process data. Multiple neurons are connected in the human brain, and the actual capacity of the brain lies in the interconnectedness of multiple neurons. As a specified generalization of ANN deep learning makes use of two or more hidden layers, which implies that a greater number of neurons are required to construct the model. A network that has more than one hidden layer, also known as two or more hidden layers, is referred to as a deep neural network, and the process of training such networks is referred to as deep learning. The research article focuses on the design of a multilayer or deep neural network presented for the target field programmable gate array (FPGA) device spartan-6 (xc6stx4-2t9g144) FPGA. The simulation is carried out using Xilinx ISE and ModelSim software. There are two hidden layers in which (2×1) multiplexer blocks are utilized for processing twenty neurons into the output of ten neurons in the first hidden layer and demultiplexers (1×2) and vice versa. The hardware utilization is estimated on FPGA to compute the performance of the deep neural hardware chip based on memory, flip flops, delay, and frequency parameters. The design is scalable and applicable to various FPGA devices, which makes the work novel. FPGA-based neuromorphic hardware acceleration platform with high speed and low power for discrete spike processing on hardware with great real-time performance.
Wireless sensor networks protocols, applications, and network-on-chip communications Ompal, Ompal; Kumar, Niraj; Mishra, Vishnu Mohan; Kumar, Adesh
IAES International Journal of Robotics and Automation (IJRA) Vol 13, No 3: September 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v13i3.pp338-350

Abstract

A wireless sensor network (WSN) is a network consisting of self-governing sensors that are deployed in space and communicate with each other using wireless technology to monitor physical or environmental variables. These networks generally include compact, inexpensive sensor nodes equipped with sensing, processing, and communication functionalities. WSNs are specifically engineered to gather data from their immediate environment, do local data processing, and subsequently communicate pertinent information either to a central hub or to other interconnected nodes within the network. Continuous research in the domain of WSNs is devoted to advancing security concerns, developing novel sensing technologies, and optimizing communication protocols. The advancements in these domains enhance the ongoing development and efficiency of WSNs. The WSNs are very important for getting information from the real world in many situations. WSNs are flexible tools for keeping an eye on and controlling different environments because they have sensor nodes, wireless communication, and distributed processing. WSNs use network-on-chip (NoC) communication architecture to connect sensor nodes. The article explains the introduction to WSN, the background of wireless communication, motivation, ZigBee protocol, and WSN applications.
Analysis of single layer artificial neural network neuromorphic hardware chip Pant, Aruna; Kumar, Adesh; Kuchhal, Piyush
IAES International Journal of Robotics and Automation (IJRA) Vol 13, No 4: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v13i4.pp495-505

Abstract

The neuromorphic architectures are hardware network systems designed with neural functions. Neural networks seen in biology serve as an inspiration for network systems. A synapse connects every node or neuron in an artificial neural network (ANN) to every other node. As in biological brains, the amplitude of the linking between nodes referred to as synaptic weights will regulate the connection. In contrast to conventional design, ANN uses many highly organized dealing pieces that work together to solve real-world issues. The design of the neuromorphic hardware chip is discussed in the paper. The target device used is a Virtex-5 Field Programmable Gate Array (FPGA) and the simulation is taken on Xilinx ModelSim software. This chip is designed for 20 neuron inputs, each of the neuron inputs is 8-bit. Each 20-neuron input is multiplied by 20 input weights and each weight is 8-bit so when these 20 input weights are multiplied by 20 neuron inputs in the multiplier it gives 16-bit output. A control logic is used in this neuromorphic hardware chip design which is used to feed multiplier output to each input of the hidden layer. The system-level outcome of the hidden layer is then given to the multiplexer which has 20 inputs and one single output. The multiplexer is used to select any of the 20 outputs of the control logic. Finally, to gain an understanding of the performance of this neuromorphic hardware chip, we have computed the hardware utilization parameters. These parameters include slices, input/output blocks (IOBs), registers used, memory, and the overall propagation delay used by the hardware chip.
2D router chip design, analysis, and simulation for effective communication Agarwal, Prateek; Kumar Garg, Tanuj; Kumar, Adesh
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 12, No 3: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v12i3.pp225-235

Abstract

The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Field programmable gate array simulation and study on different multiplexer hardware for electronics and communication Kumar, Arvind; Kumar, Adesh; Agrawal, Anurag Vijay
Computer Science and Information Technologies Vol 6, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/csit.v6i1.p28-39

Abstract

Multiplexing is the technique of transmitting two or more separate signals concurrently using a single communication channel. Multiplexing enables the augmentation of communication channels and consequently the volume of data that may be transmitted. Communication networks utilize diverse multiplexing techniques. An input multiplexer amalgamates various network signals into a singular composite signal before transmission over a shared medium. The composite signal is broken back into its component signals by a demultiplexer, when it reaches its destination, allowing further operations to utilize them separately. The design of the hardware chip depends on the configuration of the multiplexer and demultiplexer in the communication system. The work is presented as a study of the digital logic design and simulation of the different configurations of the multiplexer hardware. The performance evaluation is carried out on the different series of Xilinx field programmable gate array (FPGA) such as Spartan-6, Spartan-3E, Virtex-5, and Virtex-6 with logically checked in Xilinx ISE waveform simulator software. The current analysis of the design and simulation of different configurations of the multiplexer design helps the designers to estimate the chip performance. The novelty of the work lies in its scalable and programmable architecture fitted for specific communication systems that assess performance based on latency, frequency, and power consumption that can be further linked with communication protocols.
Analysis and implementation of computation offloading in fog architecture Gupta, Prince; Sharma, Rajeev; Gupta, Sachi; Kumar, Adesh
IAES International Journal of Robotics and Automation (IJRA) Vol 14, No 3: December 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v14i3.pp479-492

Abstract

The fast expansion of connected devices has led to an unparalleled increase in data across sectors like industrial automation, social media, environmental monitoring, and life sciences. The processing of this data presents difficulties owing to its magnitude, temporal urgency, and security stipulations. Computation offloading has arisen as a viable alternative, allowing resource-constrained devices to assign demanding work to more robust platforms, thus improving responsiveness and efficiency. This paper examines decision-making strategies for computing offloading by assessing various algorithms, including a deep neural network with deep reinforcement learning (DNN-DRL), coordinate descent (baseline), AdaBoost, and K-nearest neighbor (KNN). The performance evaluation centers on three primary metrics: system accuracy, training duration, and latency. The computation offloading mitigates these issues by transferring intricate workloads from resource-limited devices to more proficient platforms, thus enhancing efficiency and responsiveness. The evaluation examines accuracy, training duration, and latency as key parameters. The results indicate that KNN attains maximum accuracy and minimal latency, AdaBoost provides a robust balance despite increased training costs, and the baseline underperforms in both efficiency and responsiveness. These findings underscore the trade-offs between computational expense, precision, and real-time application, providing insights for forthcoming IoT and edge-computing systems.
Co-Authors Agarwal, Prateek Agrawal, Anurag Vijay Arvind Kumar, Arvind Gupta, Prince Gupta, Sachi Khastgir, Antara Kumar Garg, Tanuj Kumar, Niraj Ompal, Ompal Pant, Aruna Piyush Kuchhal Sharma, Rajeev VISHNU MOHAN MISHRA