Claim Missing Document
Check
Articles

Found 4 Documents
Search
Journal : International Journal of Electrical and Computer Engineering

FPGA Hardware Realization: Addition of Two Digital Signals Based on Walsh Transforms Zulfikar Zulfikar; Shuja A Abbasi; Abdul Rahman M Alamoud
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 6: December 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (812.677 KB)

Abstract

This paper presents hardware realization of addition of two digital signals based on Walsh transforms and inverse Walsh transforms targeted to the Xilinx FPGA Spartan 3 board. The realization utilizes Walsh Transform to convert the input data to frequency domain and the inverse Walsh transform to reconvert the data from frequency domain. The designed system is capable of performing addition, subtraction, multiplication and Arbitrary Waveform Generation (AWG). However, in the present work, the hardware realization of addition only has been demonstrated. The Clock frequency for realization into the board is supplied by an external function generator. Output results are captured using a logic analyzer. Input data to the board (system) is passed manually through the available slide switches on-board.
Design of 8-point DFT based on Rademacher Functions Zulfikar Zulfikar; Hubbul Walidainy
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 4: August 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (312.763 KB) | DOI: 10.11591/ijece.v6i4.pp1551-1559

Abstract

This paper presents a new circuit design for 8-point DFT algorithm based on product of Rademacher functions. The design has been adopted from the famous 8-point DFT decimation in time which is mainly constructs of two 4-point and four 2-point DFTs. However, the operation of the design circuit is different. It utilized the advantage of Rademacher functions simplicity. Therefore, the proposed design is constructed form the previous design 4-point DFT which is based on product of Rademacher functions [6]. Some analysis upon number types and internal connections to achieve a more efficient circuit have been conducted. As a result, instead of four, the proposed design requires only three 2-point DFT. Several output results of the design DFT have been removed since they are equal in terms of magnitude, two negative circuit are required as a compensation. Moreover, the previous 4-point DFT has been replaced to the efficient one. This circuit is special designed for non stand alone used, the circuit must be integrated inside the proposed 8-point DFT.
FPGA Realizations of Walsh Transforms for Different Transform and Word lengths into Xilinx and Altera Chips Zulfikar Zulfikar; Shuja A. Abbasi; Abdulrahman M. Alamoud
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (596.667 KB) | DOI: 10.11591/ijece.v8i6.pp4981-4994

Abstract

This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here even though this is not an apple to apple comparison. Finally, it can be concluded that Walsh transforms can be realized not only for the applications that have been done here, but it is potential can be used for other applications.
An Improved Design of Linear Congruential Generator based on Wordlengths Reduction Technique into FPGA Hubbul Walidainy; Zulfikar Zulfikar
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 1: February 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (252.781 KB) | DOI: 10.11591/ijece.v5i1.pp55-63

Abstract

This paper exposes an improved design of linear congruential generator (LCG) based on wordlengths reduction technique into FPGA. The circuit is derived from LCG algorithm proposed by Lehmer and the previous design. The wordlengths reduction technique has been developed more in order to simplify further circuit. The proposed design based on the fact that in applications only specific input data were used. Some nets connections between blocks of the circuit are ignored or truncated. Simulations either behavior or timing have been done and the results is similar to its algorithm. Four best Xilinx chips have been chosen to extract comparison data of speed and occupied area. Further comparison of occupied area in terms of flip-flop and full adder has been made. In general, the proposed design overcome the previous published LCG circuit.