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All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS) Indonesian Journal of Electrical Engineering and Computer Science
Mustapha El Alaoui
Sidi Mohamed Ben Abdellah University
Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

 1 
A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique Mustapha El Alaoui; Karim El Khadiri; Rachid El Alami; Ahmed Tahiri; Ahmed Lakhssassi; Hassan Qjidaa
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 2: April 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i2.pp1168-1179

Abstract

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%.
GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm Fatima Zahrae Zenkouar; Mustapha El Alaoui; Said Najah
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 3: June 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i3.pp2184-2193

Abstract

This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the same time, it also provides a non-binary LDPC (NB-LDPC) code set program. Furthermore, the simplified bubble check treasure event count is implemented through the use of first in first out (FIFO), which is based on an elegant design. The structure of the interpreter and the creation of the residential area he built were planned in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and simulated in MODELSIM 6.5. The combined output of the Cyclone II FPGA is combined with the simulation output.
Co-Authors Ahmed Lakhssassi Ahmed Tahiri Fatima Zahrae Zenkouar Fatima Zahrae Zenkouar Fouad Farah Hassan Qjidaa Karim El Khadiri Rachid El Alami Said Najah Said Najah