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A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique Mustapha El Alaoui; Karim El Khadiri; Rachid El Alami; Ahmed Tahiri; Ahmed Lakhssassi; Hassan Qjidaa
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 2: April 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i2.pp1168-1179

Abstract

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%.
A high efficiency and high speed charge of Li-Ion battery charger interface using switching-based technique in 180 nm CMOS technology Mustapha El Alaoui; Fouad Farah; Karim El khadiri; Ahmed Tahiri; Rachid El Alami; Hassan Qjidaa
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 12, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v12.i1.pp374-384

Abstract

In this work, the design and analysis of new Li-Ion battery charger interface using the switching-based technique is proposed for high efficiency, high speed charge and low area. The high efficiency, the lower size area and the fast charge are the more important norms of the proposed Li-Ion battery charger interface. The battery charging is completed passes to each charging mode: The first mode is the trickle charge mode (TC), the second mode is the constant current mode (CC) and the last mode is the constant voltage mode (CV), in thirty three minutes. The new Li-Ion battery charger interface is designed, simulated and layouted in Cadence software using TSCM 180 nm CMOS technology. With an input voltage VIN = 4.5 V, the output battery voltage (VBAT) may range from 2.7 V to 4.2 V and the maximum charging battery current (IBAT) is 1.7 A. The peak efficiency reaches 97% and the total area is only 0.03mm2 .
Girth aware normalized min sum decoding algorithm for shorter length low density parity check codes Abdelilah Kadi; Hajar El Ouakili; Rachid El Alami; Said Najah
Indonesian Journal of Electrical Engineering and Computer Science Vol 26, No 3: June 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v26.i3.pp1692-1700

Abstract

Recently, short block codes are in great demand due to the emergent applications requiring the transmission of a short data unit and can guarantee speedy communication, with a minimum of latency and complexity which are among the technical challenges in today’s wireless services and systems. In the context of channel coding using low density parity check (LDPC) codes, the shorter length LDPC block codes are more likely to have short cycles with lengths of 4 and 6. The effect of the cycle with the minimum size is that this one prevents the propagation of the information in the Tanner graph during the iterative process. Therefore, the message decoded by short block code is assumed to be of poor quality due to short cycles. In this work, we present a study of the evolution of the messages on check nodes during the iterative decoding process when using the LDPC decoding algorithm normalized min sum (NMS), to see the destructive effect of short cycles and justify the effectiveness of the girth aware normalized min sum (GA-NMS) decoding LDPC codes algorithm in terms of correction of the errors, particularly for the codes with short cycles 4 and 6. In addition to this, the GA-NMS algorithm is evaluated in terms of bit error rate performance and convergence behavior, using wireless regional area networks (WRAN) LDPC code, which is considered as a short block code.
New low-density-parity-check decoding approach based on the hard and soft decisions algorithms Hajar El Ouakili; Hassan Touati; Abdelilah Kadi; Younes Mehdaoui; Rachid El Alami
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 2: April 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i2.pp1639-1646

Abstract

It is proved that hard decision algorithms are more appropriate than a soft decision for low-density parity-check (LDPC) decoding since they are less complex at the decoding level. On the other hand, it is notable that the soft decision algorithm outperforms the hard decision one in terms of the bit error rate (BER) gap. In order to minimize the BER and the gap between these two families of LDPC codes, a new LDPC decoding algorithm is suggested in this paper, which is based on both the normalized min-sum (NMS) and modified-weighted bit-flipping (MWBF). The proposed algorithm is named normalized min sum- modified weighted bit flipping (NMSMWBF). The MWBF is executed after the NMS algorithm. The simulations show that our algorithm outperforms the NMS in terms of BER at 10-8 over the additive white gaussian noise (AWGN) channel by 0.25 dB. Furthermore, the proposed NMSMWBF and the NMS are both at the same level of decoding difficulty.