Noorfazila Kamal
Universiti Kebangsaan Malaysia

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Design of a low-power compact CMOS variable gain amplifier for modern RF receivers M. J. Alam; Mohammad Arif Sobhan Bhuiyan; Md Torikul Islam Badal; Mamun Bin Ibne Reaz; Noorfazila Kamal
Bulletin of Electrical Engineering and Informatics Vol 9, No 1: February 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (470.963 KB) | DOI: 10.11591/eei.v9i1.1468

Abstract

The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of more than 200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.
Design of a Current Starved Ring Oscillator Based VCO for Phase-Locked Loop Khairun Nisa’ Minhad; Zainab Kazemi; Mamun Bin IbneReaz; Jubayer Jalil; Noorfazila Kamal
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 9: September 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i9.pp6667-6672

Abstract

A design of the proposed VCO was developed for PLL in radio frequency identification (RFID) application. By using current starved ring oscillator, the designed circuit is simulated using 0.18-μm CMOS process in Mentor Graphics environment. The results show that the voltage drawn is around 5V supplied at VDD, and the product of this current and voltage has approximate 105.3 mW power consumption while the VCO generates 212 MHz at 1.4 V.