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All Journal International Journal of Electrical and Computer Engineering Indonesian Journal of Electrical Engineering and Computer Science
K. E. Kaharudin
Universiti Teknikal Malaysia Melaka
Computer Science & IT Electrical & Electronics Engineering

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Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs K. E. Kaharudin; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 4: August 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (589.391 KB) | DOI: 10.11591/ijece.v9i4.pp2863-2873

Abstract

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material Ameer F. Roslan; F. Salehuddin; A. S. M. Zain; K. E. Kaharudin; I. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 2: May 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i2.pp724-730

Abstract

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology. 
Co-Authors A. S. M. Zain Ameer F. Roslan F. Salehuddin I. Ahmad