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F. Salehuddin
Universiti Teknikal Malaysia Melaka
Computer Science & IT Electrical & Electronics Engineering

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Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs K. E. Kaharudin; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 4: August 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (589.391 KB) | DOI: 10.11591/ijece.v9i4.pp2863-2873

Abstract

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
Work function variations on electrostatic and RF performances of JLSDGM Device K K. E. Kaharudin; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan; I Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 23, No 1: July 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v23.i1.pp150-161

Abstract

This paper offers a systematic analysis on the impact of work function (WF) variations on electrostatic and radio frequency (RF) performances of nchannel junctionless strained double gate (DG) (n-JLSDGM) metal oxide semiconductor field effect transistor (MOSFET). The study has been performed under othe constant level of design parameters that operates in saturation as a transconductance amplifier, considering the dependence of electrostatic and RF performance on the variation of WF. Furthermore, this paper aims to provide physical insight into the improved electrostatic and RF performances of the proposed n-JLSDGM device. The device layout and characteristics were designed and extracted respectively via a comprehensive 2-D simulation. Device performances such as on-state current (ION), off-state current (IOFF), on-off current ratio, subthreshold swing (SS), intrinsic capacitances, dynamic power dissipation (Pdyn), cut-off frequency (fT) and maximum oscillation frequency (fmax) are intensively investigated in conjunction with WF variations.
Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material Ameer F. Roslan; F. Salehuddin; A. S. M. Zain; K. E. Kaharudin; I. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 2: May 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i2.pp724-730

Abstract

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology. 
3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect Ameer F. Roslan; F. Salehuddin; A.S. M.Zain; K.E. Kaharudin; H. Hazura; A.R Hanim; S. K Idris; B.Z. Zarina; Afifah Maheran A.H
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 3: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i3.pp1358-1365

Abstract

This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.
Co-Authors A. S. M. Zain A.R Hanim A.S. M.Zain Afifah Maheran A.H Ameer F. Roslan B.Z. Zarina H. Hazura I Ahmad I. Ahmad K K. E. Kaharudin K. E. Kaharudin K.E. Kaharudin S. K Idris