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I. Ahmad
Universiti Tenaga Nasional (UNITEN)

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Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method Ameer F. Roslan; F. Salehuddin; A.S.M. Zain; K.E. Kaharudin; I. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 3: June 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i3.pp1207-1214

Abstract

The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (ION), leakage current (IOFF), and threshold voltage (VTH) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose, VTH doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards ION and IOFF. The most dominant factor procured is the polysilicon doping tilt. The ION and IOFF obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013. 
Comparative high-k material gate spacer impact in DG-FinFET parameter variations between two structures Ameer F. Roslan; F. Salehuddin; A.S. M. Zain; K.E. Kaharudin; I. Ahmad; H. Hazura; A.R. Hanim; S.K. Idris
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp573-580

Abstract

This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio), all three materials tested being S3N4, HfO2 and TiO2 increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (VTH) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO2 has improved by 12.94% after the alteration made in terms of the overall ION and IOFF performances through the ION/IOFF ratio value obtained, as well as meeting the required value for VTH obtained at 0.464V. The ION from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.
Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material Ameer F. Roslan; F. Salehuddin; A. S. M. Zain; K. E. Kaharudin; I. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 2: May 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i2.pp724-730

Abstract

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology. 
Co-Authors A. S. M. Zain A.R. Hanim A.S. M. Zain A.S.M. Zain Ameer F. Roslan Ameer F. Roslan F. Salehuddin F. Salehuddin H. Hazura K. E. Kaharudin K.E. Kaharudin S.K. Idris