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All Journal International Journal of Electrical and Computer Engineering TELKOMNIKA (Telecommunication Computing Electronics and Control)
Ahmed Mahmood
Universiti Malaysia Pahang
Computer Science & IT Electrical & Electronics Engineering

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Effects of downscaling channel dimensions on electrical characteristics of InAs-FinFET transistor Ahmed Mahmood; Waheb A. Jabbar; Yasir Hashim; Hadi Bin Manap
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 4: August 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (781.718 KB) | DOI: 10.11591/ijece.v9i4.pp2902-2909

Abstract

In this paper, we present the impact of downscaling of nano-channel dimensions of Indium Arsenide Fin Feld Effect Transistor (InAs- FinFET) on electrical characteristics of the transistor, in particular; (i) ION/IOFF ratio, (ii) Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to simulate and compare the considered characteristics based on variable channel dimensions: length, width and oxide thickness. The results demonstrate that the best performance of InAs- FinFET was achieved with channel length = 25 nm, width= 5 nm, and oxide thickness between 1.5 to 2.5 nm according to the selected scaling factor (K = 0.125).
Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials Waheb A. Jabbara; Ahmed Mahmood; Jamil Sultan
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 20, No 1: February 2022
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v20i1.21671

Abstract

This study aims to design an optimal nano-dimensional channel of fin field effect transistor (FinFET) on the basis of electrical characteristics and constituent semiconductor materials (Si, GaAs, Ge, and InAs) to overcome issues regarding the shrinking of dimensions and ensure the best performance of FinFETs. This objective has been achieved by proposing a new scaling factor, K, to simultaneously shrink the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. A simulation-based comprehensive comparative study depending on four variable parameters (length, width, oxide thickness of the channel, and scaling factor) was carried out. The influence of changing channel dimensions on the performance of each type of FinFET was evaluated according to four electrical characteristics: i) ON-state/OFF-state current (ION/IOFF) ratio, ii) subthreshold swing (SS), iii) threshold voltage, and iv) drain-induced barrier lowering. The well-known multi-gate field-effect transistor (MuGFET) simulation tool for nanoscale MuGFET structure was utilized to conduct experimental simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for the best performance of all considered FinFET types were achieved at a minimal scaling factor K=0.125 with 5 nm length, 2.5 nm width, and 0.625 nm oxide thickness of the channel.
Co-Authors Hadi Bin Manap Jamil Sultan Waheb A. Jabbar Waheb A. Jabbara Yasir Hashim