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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics
Marco Matta
University of Rome Tor Vergata
Computer Science & IT Electrical & Electronics Engineering Engineering

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Approximated computing for low power neural networks Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Mario Patetta; Marco Re; Sergio Spanò
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 17, No 3: June 2019
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v17i3.12409

Abstract

This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò; Lorenzo Simone
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (903.688 KB) | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò; Lorenzo Simone
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (903.688 KB) | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Co-Authors Daniele Giardino Gian Carlo Cardarilli Lorenzo Simone Luca Di Nunzio Marco Re Mario Patetta Rocco Fazzolari Sergio Spanò