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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics
F. A. Bakar
Universiti Malaysia Perlis
Computer Science & IT Electrical & Electronics Engineering

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A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique A. F. Hasan; S. A. Z. Murad; F. A. Bakar
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 17, No 4: August 2019
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v17i4.12761

Abstract

A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications A. F. Hasan; S. A. Z. Murad; F. A. Bakar; T. Z. A. Zulkifli
Bulletin of Electrical Engineering and Informatics Vol 9, No 2: April 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (679.65 KB) | DOI: 10.11591/eei.v9i2.1854

Abstract

A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
Co-Authors A. F. Hasan S. A. Z. Murad T. Z. A. Zulkifli