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All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Indonesian Journal of Electrical Engineering and Computer Science
Mohd Nazrin Md Isa
Universiti Malaysia Perlis
Computer Science & IT Electrical & Electronics Engineering Engineering

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Face recognition using assemble of low frequency of DCT features Raja Abdullah Raja Ahmad; Muhammad Imran Ahmad; Mohd Nazrin Md Isa; Said Amirul Anwar
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1029.724 KB) | DOI: 10.11591/eei.v8i2.1417

Abstract

Face recognition is a challenge due to facial expression, direction, light, and scale variations. The system requires a suitable algorithm to perform recognition task in order to reduce the system complexity. This paper focuses on a development of a new local feature extraction in frequency domain to reduce dimension of feature space. In the propose method, assemble of DCT coefficients are used to extract important features and reduces the features vector. PCA is performed to further reduce feature dimension by using linear projection of original image. The proposed of assemble low frequency coefficients and features reduction method is able to increase discriminant power in low dimensional feature space. The classification is performed by using the Euclidean distance score between the projection of test and train images. The algorithm is implemented on DSP processor which has the same performance as PC based. The experiment is conducted using ORL standard face databases the best performance achieved by this method is 100%. The execution time to recognize 40 peoples is 0.3313 second when tested using DSP processor. The proposed method has a high degree of recognition accuracy and fast computational time when implemented in embedded platform such as DSP processor.
Face recognition using assemble of low frequency of DCT features Raja Abdullah Raja Ahmad; Muhammad Imran Ahmad; Mohd Nazrin Md Isa; Said Amirul Anwar
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1029.724 KB) | DOI: 10.11591/eei.v8i2.1417

Abstract

Face recognition is a challenge due to facial expression, direction, light, and scale variations. The system requires a suitable algorithm to perform recognition task in order to reduce the system complexity. This paper focuses on a development of a new local feature extraction in frequency domain to reduce dimension of feature space. In the propose method, assemble of DCT coefficients are used to extract important features and reduces the features vector. PCA is performed to further reduce feature dimension by using linear projection of original image. The proposed of assemble low frequency coefficients and features reduction method is able to increase discriminant power in low dimensional feature space. The classification is performed by using the Euclidean distance score between the projection of test and train images. The algorithm is implemented on DSP processor which has the same performance as PC based. The experiment is conducted using ORL standard face databases the best performance achieved by this method is 100%. The execution time to recognize 40 peoples is 0.3313 second when tested using DSP processor. The proposed method has a high degree of recognition accuracy and fast computational time when implemented in embedded platform such as DSP processor.
Face recognition using assemble of low frequency of DCT features Raja Abdullah Raja Ahmad; Muhammad Imran Ahmad; Mohd Nazrin Md Isa; Said Amirul Anwar
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1029.724 KB) | DOI: 10.11591/eei.v8i2.1417

Abstract

Face recognition is a challenge due to facial expression, direction, light, and scale variations. The system requires a suitable algorithm to perform recognition task in order to reduce the system complexity. This paper focuses on a development of a new local feature extraction in frequency domain to reduce dimension of feature space. In the propose method, assemble of DCT coefficients are used to extract important features and reduces the features vector. PCA is performed to further reduce feature dimension by using linear projection of original image. The proposed of assemble low frequency coefficients and features reduction method is able to increase discriminant power in low dimensional feature space. The classification is performed by using the Euclidean distance score between the projection of test and train images. The algorithm is implemented on DSP processor which has the same performance as PC based. The experiment is conducted using ORL standard face databases the best performance achieved by this method is 100%. The execution time to recognize 40 peoples is 0.3313 second when tested using DSP processor. The proposed method has a high degree of recognition accuracy and fast computational time when implemented in embedded platform such as DSP processor.
Less memory and high accuracy logarithmic number system architecture for arithmetic operations Siti Zarina Md Naziri; Rizalafande Che Ismail; Mohd Nazrin Md Isa; Razaidi Hussin
Indonesian Journal of Electrical Engineering and Computer Science Vol 23, No 3: September 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v23.i3.pp1708-1717

Abstract

Interpolation is another important procedure for logarithmic number system (LNS) addition and subtraction. As a medium of approximation, the interpolation procedure has an urgent need to be enhanced to increase the accuracy of the operation results. Previously, most of the interpolation procedures utilized the first degree interpolators with special error correction procedure which aim to eliminate additional embedded multiplications. However, the interpolation procedure for this research was elevated up to a second degree interpolation. Proper design process, investigation, and analysis were done for these interpolation configurations in positive region by standardizing the same co-transformation procedure, which is the extended range, second order co-transformation. Newton divided differences turned out to be the best interpolator for second degree implementation of LNS addition and subtraction, with the best-achieved BTFP rate of +0.4514 and reduction of memory consumption compared to the same arithmetic used in european logarithmic microprocessor (ELM) up to 51%.
Co-Authors Muhammad Imran Ahmad Raja Abdullah Raja Ahmad Razaidi Hussin Rizalafande Che Ismail Said Amirul Anwar Siti Zarina Md Naziri