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All Journal Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Indonesian Journal of Electrical Engineering and Computer Science
Labonnah Farzana Rahman
Universiti Kebangsaan Malaysia
Computer Science & IT Electrical & Electronics Engineering

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Design and Analysis of High Gain Low Power CMOS Comparator Labonnah Farzana Rahman; Mamun Bin Ibne Reaz; Wan Irma Idayu Restu; Mohammad Marufuzzaman; Lariyah Mohd Sidek
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 6, No 4: December 2018
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v6i4.816

Abstract

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2.
Advances on Low Power Designs for SRAM Cell Labonnah Farzana Rahman; Mohammad F. B. Amir; Mamun Bin Ibne Reaz; Mohd. Marufuzzaman; Hafizah Husain
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 8: August 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i8.pp6063-6082

Abstract

As the development of complex metal oxide semiconductor (CMOS) technology, fast low-power static random access memory (SRAM) has become an important component of many very large scale integration (VLSI) chips. Lot of applications preferred to use the 6T SRAM because of its robustness and very high speed. However, the leakage current has increasing with the increase SRAM size. It consumes more power while in standby condition. The power dissipation has become an importance consideration due to the increase integration, operating speeds and the explosive growth of battery operated appliances. The objective of this paper is to review and discuss several methods to overcome the power dissipation problem of SRAM. Low power SRAM can be produced with improvement in term of power dissipation during the standby condition, write operation and read operation. Discharging and charging of bit lines consumes more power during write ‘0’ and ‘1’compared to read operation. One of the methods to produce low power SRAM design is with make modification circuit at a standard 6T SRAM cell. This modification circuit will help to decrease power dissipation and leakage current. Several method was discussed in this paper for understand the method to produce low power design of SRAM cell. Recommendations for future research are also set out. This review gives some idea for future research to improve the design of low power SRAM cell.
Design of 3-Bit ADC in 0.18 µm CMOS Process Mohammad Marufuzzaman; Syarizal Z. Abidin; Mamun Bin Ibne Reaz; Labonnah Farzana Rahman
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 7: July 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i7.pp5197-5203

Abstract

Analog-to-digital converters (ADCs) are required to convert the real world analog signals into digital signals, as digital signals are more robust and easier to handle. Signal processing is increasingly being done in the digital domain along with the escalating levels of integration have forced ADC to reside on the same chip as digital circuits. The study describes the design method of 3-bit ADC using CEDEC 0.18 μm CMOS process. The designed ADC consists of; voltage divider, comparator and 7-bit encoder circuits. The pre-simulation has done with ELDO simulator with low power supply voltage (VDD) 1.8 V. The simulated results showed that the designed 3-bit ADC is able to convert analog signals to digital signals.
Co-Authors Hafizah Husain Lariyah Mohd Sidek Mamun Bin Ibne Reaz Mohammad F. B. Amir Mohammad Marufuzzaman Mohammad Marufuzzaman Mohd. Marufuzzaman Syarizal Z. Abidin Wan Irma Idayu Restu