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All Journal Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Indonesian Journal of Electrical Engineering and Computer Science

Afiq Hamzah

Universiti Teknologi Malaysia

Author-ID : 2605907

Computer Science & IT Electrical & Electronics Engineering

Published : 4 Documents Claim Missing Document

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Articles

Reliability of graphene as charge storage layer in floating gate flash memory M. Hilman Ahmad; N Ezaila Alias; Afiq Hamzah; Zaharah Johari; M. S. Z. Abidin; Norlina Paraman; M. L. Peng Tan; Razali Ismail
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 2: June 2019
Publisher : IAES Indonesian Section

This study aims to investigate the memory performances of graphene as a charge storage layer in the floating gate with difference doping concentration of n-channel and p-channel substrates using Silvaco ATLAS TCAD Tools. The simulation work has been done to determine the performance of flash memory in terms of memory window, P/E characteristics and data retention and have been validated with the experimental work done by other researchers. From the simulation data, the trend of memory window at low P/E voltage is nearly overlapped between simulation and experimental data. The memory window at ±20V P/E voltage for n-channel and p-channel flash memory cell are 15.4V and 15.6V respectively. The data retention for the n-channel flash memory cell is retained by 75% (from 15.4V to 11.6V) whereas for the p-channel flash memory cell is retained by 80% (from 15.6V to 12.5V) after 10 years of extrapolation with -1/1V gate stress which shows that p-channel flash memory cell demonstrates better data retention compared to n-channel flash memory cell.

Influence of single vacancy defect at varying length on electronic properties of zigzag graphene nanoribbons Kien Liong Wong; Mu Wen Chuan; Wee Khang Chong; Afiq Hamzah; Mohd Shahrizal Bin Rusli; Nurul Ezaila Binti Alias; Cheng Siong Lim; Michael Tan
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 2: June 2019
Publisher : IAES Indonesian Section

Graphene, identified in 2004, is now an established two-dimensional (2D) material due to its outstanding physical and electronic characteristics namely its superior electrical conductivity. Graphene is a zero-gap material that has linear dispersion with electron-hole symmetry. As pristine sheet, it cannot be utilized in digital logic application without the induction of a band gap inside the band structure. In our work, the modeling and simulation of graphene nanoribbons (GNRs) are carried out to determine its electronics properties that are benchmarked with other published simulation data. A 4-Zigzag GNRs (4-ZGNRs) under different length are utilized. A single vacancy defects is introduced at various positions inside the atomic structure. The theoretical model is implemented based on single-neighbour tight binding technique coupled with a non-equilibrium Green’s function formalism. The single vacancy defects are represented by the elimination of tight binding energies in the Hamiltonian matrix. Subsequently, these matrix elements are utilized to compute dispersion relation and density of states (DOS) through Green’s function. It is found that single vacancy defects at different positions in 4-ZGNRs’ atomic structure under varying length has no significant impacts on the sub-band structure but these vacancies impact the DOS that are computed throught Green’s function approach.

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics Mohammed Adamu Sule; Mathangi Ramakrishnan; Nurul Ezaila Alias; Norlina Paraman; Zaharah Johari; Afiq Hamzah; Michael Loong Peng Tan; Usman Ulllah Sheikh
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 2: June 2020
Publisher : IAES Indonesian Section

Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire field-effect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 1019 cm-3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversion-mode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory Farah A.Hamid; Afiq Hamzah; N. Ezaila Alias; Razali Ismail
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp765-772

Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO2 tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier. This paper presents the VARIOT concept to determine the optimum set of combination, the equivalent oxide thickness (EOT) and the low-k oxide thickness (Tox) for alternate high-k materials. Fowler-Nordheim (F-N) tunneling coefficients are also extracted for various combinations of VARIOT, where in this work ZrO2, HfO2, Al2O3, La2O3, and Y2O3 are used. The VARIOT optimization is conducted using 3-Dimensional (3D) Silicon Nanowire Field-Effect-Transistor (SiNWFET) device structure and simulated in TCAD Simulation tools. From the simulation results, it has found out that the high-k materials of La2O3 asymmetric stack is the excellent dielectric material among four (4) other dielectric materials; ZrO2, HfO2, Al2O3 and Y2O3 for EOT=4nm and Tox=1nm.

Co-Authors Cheng Siong Lim Farah A.Hamid Kien Liong Wong M. Hilman Ahmad M. L. Peng Tan M. S. Z. Abidin Mathangi Ramakrishnan Michael Loong Peng Tan Michael Tan Mohammed Adamu Sule Mohd Shahrizal Bin Rusli Mu Wen Chuan N Ezaila Alias N. Ezaila Alias Norlina Paraman Nurul Ezaila Alias Nurul Ezaila Binti Alias Razali Ismail Usman Ulllah Sheikh Wee Khang Chong Zaharah Johari

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