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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Indonesian Journal of Electrical Engineering and Computer Science
Razali Ismail
Universiti Teknologi Malaysia
Computer Science & IT Electrical & Electronics Engineering

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INVESTIGATION OF SHORT CHANNEL EFFECT ON VERTICAL STRUCTURES IN NANOSCALE MOSFET Munawar A. Riyadi; Ismail Saad; Razali Ismail
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 7, No 3: December 2009
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v7i3.591

Abstract

The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel length (Lch) is demonstrated with the help of numerical tools. The evaluation of short channel effect (SCE) parameters, i.e. threshold voltage roll-off, subthreshold swing (SS), drain induced barrier lowering (DIBL) and leakage current shows the considerable advantages as well as its thread-off in implementing the structure, in particular for nanoscale regime.
Reliability of graphene as charge storage layer in floating gate flash memory M. Hilman Ahmad; N Ezaila Alias; Afiq Hamzah; Zaharah Johari; M. S. Z. Abidin; Norlina Paraman; M. L. Peng Tan; Razali Ismail
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 2: June 2019
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (719.767 KB) | DOI: 10.52549/ijeei.v7i2.1170

Abstract

This study aims to investigate the memory performances of graphene as a charge storage layer in the floating gate with difference doping concentration of n-channel and p-channel substrates using Silvaco ATLAS TCAD Tools. The simulation work has been done to determine the performance of flash memory in terms of memory window, P/E characteristics and data retention and have been validated with the experimental work done by other researchers. From the simulation data, the trend of memory window at low P/E voltage is nearly overlapped between simulation and experimental data. The memory window at ±20V P/E voltage for n-channel and p-channel flash memory cell are 15.4V and 15.6V respectively. The data retention for the n-channel flash memory cell is retained by 75% (from 15.4V to 11.6V) whereas for the p-channel flash memory cell is retained by 80% (from 15.6V to 12.5V) after 10 years of extrapolation with -1/1V gate stress which shows that p-channel flash memory cell demonstrates better data retention compared to n-channel flash memory cell.
Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory Farah A.Hamid; Afiq Hamzah; N. Ezaila Alias; Razali Ismail
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp765-772

Abstract

Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO2 tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier. This paper presents the VARIOT concept to determine the optimum set of combination, the equivalent oxide thickness (EOT) and the low-k oxide thickness (Tox) for alternate high-k materials. Fowler-Nordheim (F-N) tunneling coefficients are also extracted for various combinations of VARIOT, where in this work ZrO2, HfO2, Al2O3, La2O3, and Y2O3 are used. The VARIOT optimization is conducted using 3-Dimensional (3D) Silicon Nanowire Field-Effect-Transistor (SiNWFET) device structure and simulated in TCAD Simulation tools. From the simulation results, it has found out that the high-k materials of La2O3 asymmetric stack is the excellent dielectric material among four (4) other dielectric materials; ZrO2, HfO2, Al2O3 and Y2O3 for EOT=4nm and Tox=1nm. 
Co-Authors Afiq Hamzah Farah A.Hamid Ismail Saad M. Hilman Ahmad M. L. Peng Tan M. S. Z. Abidin Munawar Agus Riyadi N Ezaila Alias N. Ezaila Alias Norlina Paraman Zaharah Johari