Article Per Year (5 Year)
p-Index From 2021 - 2026
0.562
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES) International Journal of Informatics and Communication Technology (IJ-ICT)
Mohanraj, Jayavelu
Unknown Affiliation
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

Published : 3 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 3 Documents
Search

 1 
Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications Kumar, Malagonda Siva; Mohanraj, Jayavelu
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 3: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i3.pp2500-2507

Abstract

As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.
Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications Siva Kumar, Malagonda; Mohanraj, Jayavelu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp307-314

Abstract

Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.
Enhancement of liner materials based on nanomaterials to promote sustainability in noise intercourse Kumar, Malagonda Siva; Mohanraj, Jayavelu
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 13, No 3: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v13i3.pp476-483

Abstract

Daily usage of devices has had a major influence on lives and existence, which would be unimaginable without them. Due to this, recent gadget dependability concerns need particular attention. PCs, hand mobile phones, and other computerized household gadgets need integrated circuits (ICs). Individual components must work together to accomplish their tasks and make the circuit operate. Hot carrier effect, oxide breakdown, and other system-level problems result from accommodating several devices in a planar IC. Vertical linking active components in one IC to another IC is a common method of three-dimensional IC integration (3D-IC). The main issue with 3D-IC adoption is electrical interference to neighboring through silicon via (TSV) and active transistors, which substantially reduces system performance. The electrical TSV (ETSV) model, which employs solely electrical signal carrying TSV, and the thermal TSV (TTSV) model, which incorporates thermal TSV during simulation, are used in this research to reduce electrical interference. The electrical signal transporting TSV to the substrate and other TSV was investigated for interference. With other models, this study also shows higher frequency regimes up to 1 THz. We found that the suggested methodology improves 3D-IC development by more than 30% by reducing electrical interference from signal-carrying TSV to other TSV.
Co-Authors Kumar, Malagonda Siva Siva Kumar, Malagonda