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All Journal International Journal of Electrical and Computer Engineering International Journal of Informatics and Communication Technology (IJ-ICT)
Kumar, Malagonda Siva
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Computer Science & IT Electrical & Electronics Engineering

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Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications Kumar, Malagonda Siva; Mohanraj, Jayavelu
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 3: June 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i3.pp2500-2507

Abstract

As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.
Enhancement of liner materials based on nanomaterials to promote sustainability in noise intercourse Kumar, Malagonda Siva; Mohanraj, Jayavelu
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 13, No 3: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v13i3.pp476-483

Abstract

Daily usage of devices has had a major influence on lives and existence, which would be unimaginable without them. Due to this, recent gadget dependability concerns need particular attention. PCs, hand mobile phones, and other computerized household gadgets need integrated circuits (ICs). Individual components must work together to accomplish their tasks and make the circuit operate. Hot carrier effect, oxide breakdown, and other system-level problems result from accommodating several devices in a planar IC. Vertical linking active components in one IC to another IC is a common method of three-dimensional IC integration (3D-IC). The main issue with 3D-IC adoption is electrical interference to neighboring through silicon via (TSV) and active transistors, which substantially reduces system performance. The electrical TSV (ETSV) model, which employs solely electrical signal carrying TSV, and the thermal TSV (TTSV) model, which incorporates thermal TSV during simulation, are used in this research to reduce electrical interference. The electrical signal transporting TSV to the substrate and other TSV was investigated for interference. With other models, this study also shows higher frequency regimes up to 1 THz. We found that the suggested methodology improves 3D-IC development by more than 30% by reducing electrical interference from signal-carrying TSV to other TSV.
Advancing semiconductor integration: 3D ICs and Perylene-N as superior liner material for minimizing TSV clamour coupling Dhal, Pradyumna Kumar; Rajesh, Murkur; Vali, Shaik Hussain; Krishna, Sadhu Radha; Kumar, Malagonda Siva; Rafi, Vempalle
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 14, No 2: August 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v14i2.pp605-613

Abstract

The semiconductor industry faces substantial challenges with planar integration (2D ICs), prompting a significant shift towards vertical IC integration, known as three-dimensional IC (3D ICs). This deliberate slant not only amplifies bandwidth and boosts system action but also effectively reduces power consumption through scaling. 3D ICs intricately coordinate IC chips by vertically stacking them and establishing electrical connections using through silicon vias (TSVs). TSV clamour coupling emerges as a critical factor influencing system performance, particularly between signalcarrying TSVs (ETSV) and victim TSVs. This study showcases significant advancements in electrical integrity by effectively minimizing clamour coupling from TSVs to the silicon substrate. This is achieved through the application of CMOS-compatible dielectric materials as liner structures. Various proposed structures have been meticulously analyzed across an assortment of parameters, encompassing electrical signals and high frequencies. Moreover, the study rigorously investigates clamour coupling across different types of TSVs, including ETSV, thermal TSV (TTSV), and heat sources. Perylene-N emerges as a standout performer among the tested liner materials, demonstrating superior clamour coupling performance across all proposed models, even at higher frequencies such as THz. In this study a novel dielectric material Perylene-N compared with the conventional SiO2 (silicon dioxide). Notably, Perylene-N exhibited a remarkable 33 dB improvement in noise coupling performance at terahertz (THz) frequencies. The results were thoroughly verified and validated in the research work.
Co-Authors Dhal, Pradyumna Kumar Krishna, Sadhu Radha Mohanraj, Jayavelu Rafi, Vempalle Rajesh, Murkur Vali, Shaik Hussain