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All Journal Bulletin of Electrical Engineering and Informatics
Tank, Hardik B.
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Electrical & Electronics Engineering

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Exploring the synergy: AI and ML in very large scale integration design and manufacturing Gonsai, Sima K.; Sheth, Kinjal Ravi; Patel, Dhavalkumar N.; Tank, Hardik B.; Desai, Hitesh L.; Rana, Shilpa K.; Bharvad, Suresh Laxmanbhai
Bulletin of Electrical Engineering and Informatics Vol 13, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v13i6.8594

Abstract

With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and development life cycle, design, testing and verification composes a substantial portion of the effort. AI and machine learning (ML) are used in many different research domains to improve predicted accuracy, automate difficult jobs, provide data-driven insights, and optimise workflows. This study aims to showcase the vital role of AI/ML in reducing complexity in VLSI chip design life cycle by automating test pattern generation and fault detection, enhancing efficiency and accuracy, and significantly reducing the time and resources needed for design verification and optimization.
Comparative analysis of meta heuristics algorithm for differential amplifier design Prajapati, Pankaj P.; Kshatriya, Anilkumar J.; Patel, Dhavalkumar N.; Gonsai, Sima K.; Tank, Hardik B.; Sheth, Kinjal R.
Bulletin of Electrical Engineering and Informatics Vol 12, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v12i6.6153

Abstract

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.
Co-Authors Bharvad, Suresh Laxmanbhai Desai, Hitesh L. Gonsai, Sima K. Kshatriya, Anilkumar J. Patel, Dhavalkumar N. Prajapati, Pankaj P. Rana, Shilpa K. Sheth, Kinjal R. Sheth, Kinjal Ravi