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All Journal Bulletin of Electrical Engineering and Informatics
Rana, Shilpa K.
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Electrical & Electronics Engineering

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Exploring the synergy: AI and ML in very large scale integration design and manufacturing Gonsai, Sima K.; Sheth, Kinjal Ravi; Patel, Dhavalkumar N.; Tank, Hardik B.; Desai, Hitesh L.; Rana, Shilpa K.; Bharvad, Suresh Laxmanbhai
Bulletin of Electrical Engineering and Informatics Vol 13, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v13i6.8594

Abstract

With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and development life cycle, design, testing and verification composes a substantial portion of the effort. AI and machine learning (ML) are used in many different research domains to improve predicted accuracy, automate difficult jobs, provide data-driven insights, and optimise workflows. This study aims to showcase the vital role of AI/ML in reducing complexity in VLSI chip design life cycle by automating test pattern generation and fault detection, enhancing efficiency and accuracy, and significantly reducing the time and resources needed for design verification and optimization.
Co-Authors Bharvad, Suresh Laxmanbhai Desai, Hitesh L. Gonsai, Sima K. Patel, Dhavalkumar N. Sheth, Kinjal Ravi Tank, Hardik B.