Garuda - Garba Rujukan Digital

Article Per Year (5 Year)

All

International Journal of Electrical and Computer Engineering

IJECE
Website

Published by Institute of Advanced Engineering and Science

ISSN : 20888708 EISSN : 27222578 DOI : -

Core Subject : Science, Engineering,

Computer Science & IT Electrical & Electronics Engineering

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.

Arjuna Subject : Ilmu Komputer (semua kategori) - Ilmu Komputer (Lain-Lain)

Articles 6,301 Documents

183 184 185 186 187

Fuzzy based Power Flow control of Two Area Power System K Manickavasagan
International Journal of Electrical and Computer Engineering (IJECE) Vol 2, No 1: February 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (443.545 KB)

This paper deals with the novel approach of fuzzy based power flow control of two area power system. Interconnected operation enables utilities to share the generation from one area to other areas. In each area, all the generators are synchronized at same frequency. The change in system load within the area causes frequency deviation in the generating buses and tie line error in the tie lines connecting neighboring areas. The control of interconnected power system is achieved by Automatic Generation Control (AGC), which maintains the balance between generation and load. In this paper, the components of AGC, frequency deviation (DF), tie line error (DPtie) and the output change in generations (DPgi) are calculated by steady state power flow analysis using decoupled Newton Raphson method. The control action is performed by conventional method using participation factor and Fuzzy Logic Controller (FLC). The DF and DPtie are the inputs to the conventional controller and Fuzzy Logic Controller (FLC). The proposed method is tested with modified IEEE 30 bus system and the results are compared. Analysis reveals that FLC is quite capable of suppressing the frequency deviation and tie line error effectively as compared to that obtained with conventional controller.DOI:http://dx.doi.org/10.11591/ijece.v2i1.219

A Comprehensive Survey on Exiting Solution Approaches towards Security and Privacy Requirements of IoT Rajani Chetan; Ramesh Shahabadkar
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 4: August 2018
Publisher : Institute of Advanced Engineering and Science

‘Internet of Things (IoT)’emerged as an intelligent collaborative computation and communication between a set of objects capable of providing on-demand services to other objects anytime anywhere. A large-scale deployment of data-driven cloud applications as well as automated physical things such as embed electronics, software, sensors and network connectivity enables a joint ubiquitous and pervasive internet-based computing systems well capable of interacting with each other in an IoT. IoT, a well-known term and a growing trend in IT arena certainly bring a highly connected global network structure providing a lot of beneficial aspects to a user regarding business productivity, lifestyle improvement, government efficiency, etc. It also generates enormous heterogeneous and homogeneous data needed to be analyzed properly to get insight into valuable information. However, adoption of this new reality (i.e., IoT) by integrating it with the internet invites a certain challenges from security and privacy perspective. At present, a much effort has been put towards strengthening the security system in IoT still not yet found optimal solutions towards current security flaws. Therefore, the prime aim of this study is to investigate the qualitative aspects of the conventional security solution approaches in IoT. It also extracts some open research problems that could affect the future research track of IoT arena.

Path Loss Modeling of WLAN and WiMAX Systems Imran Israr; Mahmood Ashraf Khan; Shahzad A. Malik; Shahid A. Khan; Mustafa Shakir
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 5: October 2015
Publisher : Institute of Advanced Engineering and Science

With the advancement in technology, there was need for efficient and high speed internet through which we could have access to multiple networks as per the user requirement. WLAN met this need to some extent but, due to its low range it was not recommended commercially. With the introduction of WiMAX there was an emerging need to select the best network amongst WiMAX or WLAN depending upon the user location. Pathloss with respect to these particular networks also needs to be compared. In this paper we compare the pathloss modelling for WiMAX and WLAN systems. Different Models have been compared with each other to know which model performs better by keeping same simulation environment. Path Loss models used for WLAN are Okumura, Hata, Cost-231 and Free Space Path Loss whereas models used for WiMAX are Free Space Path Loss, Okumura-Hata, Cost231-Hata and Stanford University Interim. In case of WiMAX three different scenarios Urban, Sub-Urban and Rural is considered where as in case of WLAN only outdoor environment is considered. With the Path Loss comparison, power received for these two technologies; WiMAX, and WLAN is also simulated. MATLAB is the tool used for simulations. Antenna Specifications for WiMAX and WLAN is kept same for all simulation environments.

Optimized memory model for hadoop map reduce framework Archana Bhaskar; Rajeev Ranjan
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 5: October 2019
Publisher : Institute of Advanced Engineering and Science

Map Reduce is the preferred computing framework used in large data analysis and processing applications. Hadoop is a widely used Map Reduce framework across different community due to its open source nature. Cloud service provider such as Microsoft azure HDInsight offers resources to its customer and only pays for their use. However, the critical challenges of cloud service provider is to meet user task Service level agreement (SLA) requirement (task deadline). Currently, the onus is on client to compute the amount of resource required to run a job on cloud. This work present a novel memory optimization model for Hadoop Map Reduce framework namely MOHMR (Optimized Hadoop Map Reduce) to process data in real-time and utilize system resource efficiently. The MOHMR present accurate model to compute job memory optimization and also present a model to provision the amount of cloud resource required to meet task deadline. The MOHMR first build a profile for each job and computes memory optimization time of job using greedy approach. Experiment are conducted on Microsoft Azure HDInsight cloud platform considering different application such as text computing and bioinformatics application to evaluate performance of MOHMR of over existing model shows significant performance improvement in terms of computation time. Experiment are conducted on Microsoft Azure HDInsight cloud. Overall, good correlation is reported between practical memory optimization values and theoretical memory optimization values.

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes A. Boudaoud; M. El Haroussi; E. Abdelmounim
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.

Finding the shortest path in a graph and its visualization using C# and WPF Radoslav Mavrevski; Metodi Traykov; Ivan Trenchev
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 2: April 2020
Publisher : Institute of Advanced Engineering and Science

The shortest path problem is a classic problem in mathematics and computer science with applications in Economics (sequential decision making, analysis of social networks, etc.). The presented work is an example of realizing and applying of Dijkstra's algorithm to find the shortest path between two vertices in a connected, undirected graph, which is often a solved problem at a time annual International Olympiad in Informatics. For this purpose, are used the technologies, .NET 4.0, Visual Studio 2010, and WPF for the graphical user interface. The implemented program allows drawing an undirected graph, visualizing the shortest path between two vertices and finding its value. This software is a valuable tool for the study of Dijkstra's algorithm and is a great pedagogic instrument. All figures of path visualization included in this paper are actual screenshots of our visualization program.

Producer Mobility Support Schemes for Named Data Networking: A Survey Muktar Hussaini; Shahrudin Awang Nor; Amran Ahmad
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Mobile devices connectivity and data traffic growth requires scalable and efficient means of data distribution over the Internet. Thus, influenced the needs for upgrading or replacing the current Internet architecture to cater the situation as Named Data Networking (NDN) was proposed. NDN is clean-slate Internet architecture, proposed to replace IP with hierarchical named content that utilizes route aggregation to improve scalability and support mobility. Although, NDN provides supports for content consumer mobility with the help of catching capabilities, however, content producer faces many problems similar to mobility in IP architecture, such as, long handoff delay, unnecessary Interest packet losses and high bandwidth utilization. Hence, many concepts and schemes were proposed to address these problems. This paper reviewed and conceptually analyzed the schemes based on their fundamental design that broadly categorized into indirection-based approach, mapping-based approach, locator-based approach and control/data plane-based approach. In the review analysis, mapping-based approach schemes provide optimal path for packets delivery, high handoff delay Indirection-based and locator-based approach schemes provide normal handoff delay, but introduces tiangular routing path. The control/data plane-based approach schemes provide sub-optimal routing path and high handoff delay. The paper provided both strength and weakness of each scheme for further research.

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance Munawar A Riyadi; Irawan D Sukawati; Teguh Prakoso; Darjat Darjat
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 2: April 2016
Publisher : Institute of Advanced Engineering and Science

The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.

Sliding-Mode Controller Based on Fractional Order Calculus for a Class of Nonlinear Systems Noureddine Bouarroudj; Djamel Boukhetala; Fares Boudjema
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 5: October 2016
Publisher : Institute of Advanced Engineering and Science

This paper presents a new approach of fractional order sliding mode controllers (FOSMC) for a class of nonlinear systems which have a single input and two outputs (SITO). Firstly, two fractional order sliding surfaces S1 and S2 were proposed with an intermediate variable z transferred from S2 to S1 in order to hierarchy the two sliding surfaces. Secondly, a control law was determined in order to control the two outputs. A sliding control stability condition was obtained by using the properties of the fractional order calculus. Finally, the effectiveness and robustness of the proposed approach were demonstrated by comparing its performance with the one of the conventional sliding mode controller (SMC), which is based on integer order derivatives. Simulation results were provided for the cases of controlling a ball-beam and inverted pendulum systems.

Low bit Rate Video Quality Analysis Using NRDPF-VQA Algorithm Subrahmanyam CH; Venkata Rao D; Usha Rani N
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 1: February 2015
Publisher : Institute of Advanced Engineering and Science

In this work, we propose NRDPF-VQA (No Reference Distortion Patch Features Video Quality Assessment) model aims to use to measure the video quality assessment for H.264/AVC (Advanced Video Coding). The proposed method takes advantage of the contrast changes in the video quality by luminance changes. The proposed quality metric was tested by using LIVE video database. The experimental results show that the new index performance compared with the other NR-VQA models that require training on LIVE video databases, CSIQ video database, and VQEG HDTV video database. The values are compared with human score index analysis of DMOS.

Page 185 of 631 | Total Record : 6301

183 184 185 186 187

Filter by Year

2011 2026

Filter By Issues

All Issue Vol 16, No 1: February 2026 Vol 15, No 6: December 2025 Vol 15, No 5: October 2025 Vol 15, No 4: August 2025 Vol 15, No 3: June 2025 Vol 15, No 2: April 2025 Vol 15, No 1: February 2025 Vol 14, No 6: December 2024 Vol 14, No 5: October 2024 Vol 14, No 4: August 2024 Vol 14, No 3: June 2024 Vol 14, No 2: April 2024 Vol 14, No 1: February 2024 Vol 13, No 6: December 2023 Vol 13, No 5: October 2023 Vol 13, No 4: August 2023 Vol 13, No 3: June 2023 Vol 13, No 2: April 2023 Vol 13, No 1: February 2023 Vol 12, No 6: December 2022 Vol 12, No 5: October 2022 Vol 12, No 4: August 2022 Vol 12, No 3: June 2022 Vol 12, No 2: April 2022 Vol 12, No 1: February 2022 Vol 11, No 6: December 2021 Vol 11, No 5: October 2021 Vol 11, No 4: August 2021 Vol 11, No 3: June 2021 Vol 11, No 2: April 2021 Vol 11, No 1: February 2021 Vol 10, No 6: December 2020 Vol 10, No 5: October 2020 Vol 10, No 4: August 2020 Vol 10, No 3: June 2020 Vol 10, No 2: April 2020 Vol 10, No 1: February 2020 Vol 9, No 6: December 2019 Vol 9, No 5: October 2019 Vol 9, No 4: August 2019 Vol 9, No 3: June 2019 Vol 9, No 2: April 2019 Vol 9, No 1: February 2019 Vol 8, No 6: December 2018 Vol 8, No 5: October 2018 Vol 8, No 4: August 2018 Vol 8, No 3: June 2018 Vol 8, No 2: April 2018 Vol 8, No 1: February 2018 Vol 7, No 6: December 2017 Vol 7, No 5: October 2017 Vol 7, No 4: August 2017 Vol 7, No 3: June 2017 Vol 7, No 2: April 2017 Vol 7, No 1: February 2017 Vol 6, No 6: December 2016 Vol 6, No 5: October 2016 Vol 6, No 4: August 2016 Vol 6, No 3: June 2016 Vol 6, No 2: April 2016 Vol 6, No 1: February 2016 Vol 5, No 6: December 2015 Vol 5, No 5: October 2015 Vol 5, No 4: August 2015 Vol 5, No 3: June 2015 Vol 5, No 2: April 2015 Vol 5, No 1: February 2015 Vol 4, No 6: December 2014 Vol 4, No 5: October 2014 Vol 4, No 4: August 2014 Vol 4, No 3: June 2014 Vol 4, No 2: April 2014 Vol 4, No 1: February 2014 Vol 3, No 6: December 2013 Vol 3, No 5: October 2013 Vol 3, No 4: August 2013 Vol 3, No 3: June 2013 Vol 3, No 2: April 2013 Vol 3, No 1: February 2013 Vol 2, No 6: December 2012 Vol 2, No 5: October 2012 Vol 2, No 4: August 2012 Vol 2, No 3: June 2012 Vol 2, No 2: April 2012 Vol 2, No 1: February 2012 Vol 1, No 2: December 2011 Vol 1, No 1: September 2011 More Issue

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name
Tole Sutikno

Contact Email
ijece@iaesjournal.com

Phone
-

Journal Mail Official
ijece@iaesjournal.com

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name Tole Sutikno

Contact Email ijece@iaesjournal.com

Phone -

Journal Mail Official ijece@iaesjournal.com

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
Tole Sutikno

Contact Email
ijece@iaesjournal.com

Phone
-

Journal Mail Official
ijece@iaesjournal.com

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA