International Journal of Power Electronics and Drive Systems (IJPEDS)
International Journal of Power Electronics and Drive Systems (IJPEDS, ISSN: 2088-8694, a SCOPUS indexed Journal) is the official publication of the Institute of Advanced Engineering and Science (IAES). The scope of the journal includes all issues in the field of Power Electronics and drive systems. Included are techniques for advanced power semiconductor devices, control in power electronics, low and high power converters (inverters, converters, controlled and uncontrolled rectifiers), Control algorithms and techniques applied to power electronics, electromagnetic and thermal performance of electronic power converters and inverters, power quality and utility applications, renewable energy, electric machines, modelling, simulation, analysis, design and implementations of the application of power circuit components (power semiconductors, inductors, high frequency transformers, capacitors), EMI/EMC considerations, power devices and components, sensors, integration and packaging, induction motor drives, synchronous motor drives, permanent magnet motor drives, switched reluctance motor and synchronous reluctance motor drives, ASDs (adjustable speed drives), multi-phase machines and converters, applications in motor drives, electric vehicles, wind energy systems, solar, battery chargers, UPS and hybrid systems and other applications.
Articles
2,660 Documents
<![CDATA[Assessing annual energy production using a combination of lidar and mast measurement campaigns ]]>
<![CDATA[Mkhaitari, Rachid]]>;
<![CDATA[Mir, Yamina]]>;
<![CDATA[Zazoui, Mimoun]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp2398-2408
<![CDATA[The current study evaluates the wind potential at early stage of wind project using met mast and lidar. The wind data obtained from a met mast located away from the turbines can be hindered by obstacles, leading to limited coverage and height, it negatively impacting the project's performances. To address the above limitations, the study suggests implementing a secondary measurement approach utilizing Lidars in various locations to cover the full study area. This work assesses the two measurements campaign and compares the wind potential evaluated with data measured by met mast and lidars. The simulations of two wind data base are quantified referring to the main key performance indicators for a project of total capacity of 140MW. The results show significant improvement in gross and net production for all exceedance scenarios, with 2% increase on the P90, and an improvement in the annual capacity factor by 1.09%. The use of Lidar data referenced to a met mast leads to accurate and bankable data, with the advances of cost and logistics, Lidars helps in layout configuration and performance evaluation.]]>
<![CDATA[A low power and high speed 45 nm CMOS dynamic comparator with low offset ]]>
<![CDATA[Brindha, Kulothungan]]>;
<![CDATA[Manjula, Jothilingam]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp2293-2300
<![CDATA[The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data converters. Moreover, addressing the offset voltage of comparators becomes crucial for achieving accurate signal conversion. To fulfill this need, a novel dynamic comparator has been designed, featuring high-speed operation, low-power consumption, and minimal offset. The circuit comprises a pre-amplifier with a charge pump, followed by a decision circuit and an output stage. Through simulations, the comparator has demonstrated low power consumption of 15.04 µW, a delay of 80.51 ps, and an extremely low offset voltage of 8 µV. These characteristics make it highly suitable for data converters. The comparator operates at a clock frequency of 1 GHz and a supply voltage of 1 V, and the simulation was conducted using the Cadence Virtuoso tool in a 45 nm CMOS technology.]]>
<![CDATA[Novel complementary Sziklai pair based high gain low noise small-signal amplifiers ]]>
<![CDATA[Shukla, SachchidaNand]]>;
<![CDATA[Arshad, Syed Shamroz]]>;
<![CDATA[Srivastava, Geetika]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp2283-2292
<![CDATA[A new paired configuration of opposite polarity BJTs, the “complementary Sziklai pair” is introduced in the series of multi-BJT-based devices like Darlington and Sziklai pair, and its viability is tested in small-signal common emitter (CE) and common collector (CC) amplifier configurations. The Darlington and Sziklai both face the problem of poor frequency response at a higher frequency which is addressed by the proposed configuration. The proposed pair with CE amplifier holds class-A amplification property with a high voltage gain of 200.05, a high current gain of 11.62, wider bandwidth of 1.64 MHz, and a low THD of 1.29E-6%, hence supports the potential of wide applicability in analog communication. Similarly, the proposed pair with CC configuration produces approximately a unit current gain of 0.99 with wider bandwidth of 1.90 MHz and low THD of 1.76E-6%, therefore it can be used as a current buffer in a generalized current follower circuit. Conclusively, the device structure of this new BJT pair may be considered the third consecutive member of the series of Darlington pair and Sziklai pair. The layout of the proposed CE and CC amplifier occupy small areas of 158.30 μm2 (10.23×15.47 μm) and 141.16 μm2 (10.20×13.84 μm) respectively in 180 nm process technology.]]>
<![CDATA[An investigation of piezoelectric tile with drop test technique for energy harvesting application ]]>
<![CDATA[Anis Maisarah Mohd Asry]]>;
<![CDATA[Farahiyah Mustafa]]>;
<![CDATA[Sim Sy Yi]]>;
<![CDATA[Maizul Ishak]]>;
<![CDATA[Aznizam Ahmad]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 3: September 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i3.pp1633-1638
<![CDATA[This paper present test and analyses of piezoelectric transducers tile with drop test technique. This piezoelectric tile was tested together with bending mechanism. The bending mechanism was designed using SolidWork software and manufactured by employing 3D printer technology to conduct the evaluation. The piezoelectric transducers connected in a parallel configuration and inserted in piezoelectric tile together with bending mechanism. The drop test employed to test this piezoelectric tile with various loads and speeds. This test conducted based on free fall concept. A wooden box used as a guide to drop an object onto the piezoelectric tile. The various weight load released at a fixed height with different speeds. The output power generated based on the weight and speed of the object were recorded with average force applied on piezoelectric transducer. The highest output power generated was 634.54 µW when 6 kg load released at 2 drop/s with 1.89 N average force applied on each piezoelectric transducer. The lowest output power generated was 6.28 µW when 1 kg load released at 0.5 drop/s with 0.22 N average force applied. The results showed good output power of the piezoelectric transducer was generated for energy harvesting application.]]>
<![CDATA[Performance enhancement of distance relay in presence of unified power flow controller ]]>
<![CDATA[Hiba Nadhim A. Al-Kaoaz]]>;
<![CDATA[Ahmed Nasser B. Alsammak]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 3: September 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i3.pp1577-1588
<![CDATA[The characteristics of the distance relay are devised based on online and fault impedance. The relay uses fault information to react to the expected state; however, integrating the grid with a unified power flow controller (UPFC) might stop the relay from fault-triggered operations, requiring altered relay characteristics. Building relay tripping parameters are among the critical challenges that must be addressed for transmission line distance relays because current transmission networks face higher stress regarding power system operation. Furthermore, the use of flexible AC transmission systems (FACTS) instruments at the transmission level adversely affects distance relay performance due to impedance differences. The UPFC is among the essential FACTS instruments; it comprises shunt and series converters to alter the apparent relay impedance; hence, it was considered for this study, where a test system during fault was assessed to demonstrate the output of the distance relay before and after using the UPFC. MATLAB was used to build scenarios demonstrating the effect of a UPFC located in the transmission line's midsection or end or not using the UPFC. This research offers an analytical technique to determine the probable effects of UPFC on distance relay characteristics. The outcomes provide new relay characteristics for several fault resistances and locations for fault-specific impedance trajectory reactions.]]>
<![CDATA[Comparative study between PI and SMC controllers for DFIG using fuzzy wind power estimator ]]>
<![CDATA[Atef Jemmali]]>;
<![CDATA[Khaled Elleuch]]>;
<![CDATA[Hafedh Abid]]>;
<![CDATA[Ahmed Toumi]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 3: September 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i3.pp1748-1758
<![CDATA[In this paper, we are interested in the control of the rotor current of the doubly feed induction generator (DFIG), that is used in wind turbines. In this context, we present a comparative study between two types of controllers. The first is based on a classic PI proportional-integral control, while the second is based on the SMC sliding control. The command chain uses a fuzzy estimator of the wind power, which makes it possible to determine the reference speed of DFIG. The system includes essentially a turbine, two converters, one on the rotor side and the other on the grid side, and a filter. The grid-side converter is used to maintain a constant DC bus voltage and to control rotor reactive power. The rotor side converter is used to control the speed of the DFIG to guarantee maximum power extracted from the turbine. In addition, this converter allows controlling the reactive power through the control of the rotor current according to the axis "d" of the frame linked to the rotating field. The simulation results show the effectiveness of sliding mode control (SMC) for the considered system.]]>
<![CDATA[Design and analysis of a high-gain dual-input single-output DC-DC converter for hybrid energy systems applications ]]>
<![CDATA[Bharathi, Botta Venkata Vara Lova Kala]]>;
<![CDATA[Satish, Raavi]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 3: September 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i3.pp1534-1543
<![CDATA[The high gain converters are one among the proven topologies that are found attractive for industrial and commercial applications. They deal with high power ratings like automobile headlamps, energy backup systems, and fuel cell electric vehicles (FCEV). In literature, most of the topologies were used a single duty ratio. This may not be reliable for high-duty cycle operation because to improve the voltage gain, the components will be increases. This paper proposes the time-sharing concept based on the non-isolated high step-up dc-dc converter. With the parallel-charged and series-discharged inductors, the proposed converter can produce high output voltage gains. The effectiveness of the proposed circuit configuration is verified in MATLAB/Simulink and the results are corroborated by theoretical analysis.]]>
<![CDATA[Design of the transmitter coil used in wireless power transfer system based on genetic algorithm ]]>
<![CDATA[Konghirun, Mongkol]]>;
<![CDATA[Nutwong, Supapong]]>;
<![CDATA[Sangswang, Anawach]]>;
<![CDATA[Hatchavanich, Nattapong]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp2307-2318
<![CDATA[Performance of the wireless power transfer (WPT) system relies on the physical dimensions of the coupled coil, which should be optimally designed to meet required system performance and reduce the operating cost. This paper presents an optimal design based on genetic algorithm (GA) for the transmitter coil used in wireless power transfer system. Physical parameters of the circular flat spiral coil, including wire’s cross-sectional area, coil’s inner diameter, coil’s outer diameter, coil’s turn number, and space between each turn of the coil are considered. The design objective is to minimize the total wire length required by the coil subjected to both linear and nonlinear constraints. The design process is implemented on MATLAB optimization toolbox which is simple and accurate. The validity of proposed optimal coil design is verified by the experiment, which indicates that total wire length of the optimized coil can be reduced by 5.5 percent compared to the conventional coil without sacrificing the system performance. System efficiency obtained from the optimized coil can be improved up to 8.32 percent.]]>
<![CDATA[Controlling the significance of BLDC motor internal faults using dual examine algorithm in electric vehicle applications ]]>
<![CDATA[Gaurav, Gaurav]]>;
<![CDATA[Nakka, Jayaram]]>;
<![CDATA[Obulesu, Dakka]]>;
<![CDATA[Arandhakar, Sairaj]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp1946-1954
<![CDATA[This paper presents dual examine algorithm (DEA) to reduce residual error as well as to provide accurate phase currents without any distortion for a closed loop brushless direct current (BLDC) motor of an electric vehicle (EV). The underlying technology of DEA is a hybrid of the tabu search optimization (TSO) method and the genetic algorithm (GA). During closed loop operation of BLDC motor residual error is introduced by the discrepancy between the actual and reference speed, and the phase current distortion lowers the efficiency of the machine as a result machine performance is degraded. To address these issues, GA algorithm calculates the necessary parameters for the controller to produce precise current without distortion based on stator phase currents, and the suggested TSO algorithm limits the repeated operations in the PID controller to reduce the residual error to the greatest degree feasible. After primary examining, dual examine process initiate the transposing operation such as TSO is used to prove and calculate the phase current controller parameters, and GA is used to correct for remaining inaccuracy. To validate the proposed DEA algorithm is compared with advanced particle swarm optimization (APSO). The results verified the superiority of proposed DEA algorithm using MATLAB/Simulink platform.]]>
<![CDATA[Modified instantaneous power theory control of dynamic voltage restorer powered by photovoltaic system ]]>
<![CDATA[Asiri, Yousef]]>;
<![CDATA[Al-Gahtani, Saad F.]]>;
<![CDATA[Irshad, Shaik Mohammad]]>
<![CDATA[ International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijpeds.v14.i4.pp2418-2432
<![CDATA[Power quality issues have become widespread due to nonlinear electronic converters and loads. Nonlinear components in the power system hamper the power quality, network efficiency and voltage regulation. The power quality issues like sag, swell, and voltage unbalance can be reduced by employing a dynamic voltage restorer (DVR). DVR provides the compensating power from a DC source to minimize the effect of sag, swell, and voltage unbalance. This article presents a power system with DVR using a photovoltaic system (PV) as a DC source instead of a conventional battery source. This article proposes a modified instantaneous power (PQ) control technique to generate the reference signal of load voltage to assure the DVR's superior performance. This modified technique uses an anti-aliasing filter to generate a reference signal. This proposed technique is tested under extreme power quality issues of 80% sag, 20% sag, 120% swell, 170% swell, and voltage unbalance. The DVR is modeled and simulated using MATLAB/Simulink. A comparison is made between the traditional and modified PQ methods from the obtained results. The analyzed results under severe power quality issues suggest that the proposed P-Q control technique is a preferable option for the DVR with PV as a DC power supply.]]>
