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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

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Articles 5 Documents

Search results for , issue "Vol 2, No 1: March 2013" : 5 Documents clear

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT) Abderrezak Marzaki; V. Bidal; R. Laffont; W. Rahajandraibe; J-M. Portal; R. Bouchakour
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages VTH- (low switching voltage) and VTH+ (high switching voltage).

Design and Development of Stream Processor Architecture for GPU Application Using Reconfigurable Computing Sanket Dessai; Krishna Bhushan Vutukuru
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters.For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed of stream processor unit has been carried out in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.The simulated execution time of 8-bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz.

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication Sachin B. Jadhav; Jayamala K. Patil; Ramesh T. Patil
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines P.Radhika Ramya; Y.Sudha Vani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

The Reversible logic plays an important role to obtain the minimal energy dissipation. It is the main requirement in the low power digital design. To implement a reversible function some additional lines are required. Sometimes it is more than the primary inputs which leads to increased size of the circuit. Hence the reducing the number of circuit lines is one of the major criterion in reversible logic. The general idea is to merge the garbage output lines with appropriate constant input lines. In this work, Toffoli gate implementation of BCD adder and press gate implementation of BCD adder is taken and an optimization algorithm has been applied to reduce the number of lines in the circuit. The kit used to implement the design is Vertex5 in which both the area and delay are analyzed.

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC Arash Farhadi Beldachi; Mohammad Hosseinabady; Jose Luis Nunez-Yanez
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

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