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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 5 Documents

Search results for , issue "Vol 2, No 2: July 2013" : 5 Documents clear

Crosstalk Minimization in VLSI Interconnects Damanpreet Kaur; V. Sulochana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

Crosstalk noise is often induced in long interconnects running parallel to each other .There arises a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. So in this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Prelayout simulations for crosstalk are carried out for different techniques at 90nm technology nodes using cadence. The influences of these techniques are analyzed and it is found that crosstalk is reduced upto 57%.

A Novel Evolutionary Method for Designing Optimized Multifunctional Logic Modules Mehdi Anjomshoa; Ali Mahani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area.

CO Pollution Warning System for Indoor Parking Area Using FPGA Prima Dewi Purnamasari; Evan G. Sumbayak; Vicky Dwi Kurniawan; RR. Wulan Apriliyanti
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

From some compounds used as parameters in air pollution-such as O3, Particulate Materials, CO, NO2, SO2 and Pb-CO is the most common cause of poisoning accidents. Indoor parking area is one sample of potential area for CO pollution. However, according to the scientific nature of CO-tasteless, colorless, and odorless-people exposed to CO are usually not aware that s/he exposed to dangerous levels of CO. This research aimed to make a prototype of an embedded system that can monitor air pollution, give an effective warning and it should be affordable. The prototype of CO air pollution alert system has been successfully built using FPGA Xilinx Spartan 3E as the major component. Sensor Hanwei MQ7 used in this prototype has been tested in a simulation box using cigarette smoke as CO pollutant and the reading result has met the characteristic curve in the datasheet. The system interface has met user satisfaction with MOS value 4.31 from 5 scales. Based on the response time testing, we conclude that FPGA is suitable to be used in a system that performs fast parallel processing based on logical actions from the input given.

Design of Mesh and Torus Topologies for Network-On-Chip Application Sonal S. Bhople; M. A. Gaikwad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

Network-on-Chip (NoC) is a general purpose on-chip communication concept that offers high throughput, which is the basic requirement to deal with complexity of modern systems. In Network on chip topology design is one of the significant factors that affect the net delay of the system. In this paper mesh topology and torus topology are compared in terms of network delay for a given NOC application using Xillinc 9.1c.

Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5 Shruthi AV; Electa Alice; Mohammed Bilal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

A new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained.

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Contact Name
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Journal Mail Official
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Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA