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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 5 Documents

Search results for , issue "Vol 3, No 1: March 2014" : 5 Documents clear

Decision Based Median Filter algorithm using Resource Optimized FPGA to Extract Impulse Noise Rutuja Nandkumar Kulkarni; Pradip C Bhaskar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents an accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by using median value when other pixel values, 0’s or 255’s are present in the selected window and when all the pixel values are 0’s and 255’s then the noise pixel is replaced by mean value of all the elements present in the selected window. Similarly algorithm checks for five different conditions to preserve image details, object boundary in high level of noise densities. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Implementation of High Speed Self Switching Frequency Agile RADAR K Jansi Lakshmi; K Surya Narayana Reddy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

The radar has to resist diversified jamming; High Speed self-adaptive frequency agility is an important and effective function for radars to resist jamming. The procedure to achieve this function are described, and the function is realized with FPGA using Hardware description Language, the validity is proved by on- line sampling and simulation. The High speed self-adaptive frequency agility module can analyze the type of jamming to select transmitting frequency to avoid the frequencies which have interference, under frequency diversity and fixed frequency, respectively. The general application on a searching radar shows that the module has good real-time and anti- jamming capacity.

Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing Anshuman Sharma; Abdul Hafeez Syed; Midhun M; M R Raghavendra
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented.

Implementation of LOCO-I Lossless Image Compression Algorithm for Deep Space Applications P. Praveena
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

Present emerging trend in space science applications is to explore and utilize the deep space. Image coding in deep space communications play vital role in deep space missions. Lossless image compression has been recommended for space science exploration missions to retain the quality of image. On-board memory and bandwidth requirement is reduced by image compression. Programmable logic like field programmable gate array (FPGA) offers an attractive solution for performance and flexibility required by real time image compression algorithms. The powerful feature of FPGA is parallel processing which allows the data to process quicker than microprocessor implementation. This paper elaborates on implementing low complexity lossless image compression algorithm coder on FPGA with minimum utilization of onboard resources for deep space applications.

FPGA Based Firewall using Embedded Processor for Vulnarability Packet Detection Mohamed Yousuf Hasan; Poornima V.P; Sujendran S; Karthikraja D
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

This paper describes the design of high performance packet filtering firewall using embedded system. An FPGA (field programmable gate array) platform has been used for implementation and analysing the network firewall. It is capable of accepting real time changes. This network security application has an ability to perform powerful protection against unwanted data packets such as virus attack, spam in e-mails, hackers, worms, spyware unauthorized contents. However the firewalls don’t address the difficulty of unwanted data packets intrusion. The ultimate aim of this work is to create a systematic way of approach for unwanted packets discard in a network system. We use a specially trained algorithms such as Wu-manber algorithms (high performance, multi-pattern matching), bloom filter algorithm (space efficient data structure for testing an element in the set.Our design is mainly based on machine learning and artificial intelligence. This gives a high efficiency, improved performance and high ability of packet detection with less contribution of time in an effective way.

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