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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 7 Documents

Search results for , issue "Vol 7, No 1: March 2018" : 7 Documents clear

Design and Development of IP for Modified Haar Wavelet Transform (MHWT) Image Fusion using FPGA Sumant S Yaliagr; Sanket Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

The fast growth in the field of digital imaging applications in remote sensing, bio medical and other satellite applications had created an architecture studies for image fusion in capable to store large amount of data and process. An algorithm considered for the process of image fusion for implementation of FPGA is Modified Haar Wavelet Transform (MHWT) based image fusion where at the time four pixels are consider in calculation of different bands as compared to conventional Haar wavelet based image fusion. The process of modification uses far less memory and computation power. The FPGA implementation of MHWT based image fusion is done on Digilent development board with Spartan 6 series FPGA. The architecture is developed in VHDL. The timing analysis is done and report is obtained for I/O interactions, memory units etc. The architecture is made to run in cosimulation with Simulink. The design is tested with different kinds of images and run successfully. The visual analysis of the resultant fused image is achived and observed.

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications M. Parvathi; N. Vasantha; K. Satya Prasad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder Saravanakumar Saravanakumar; Vijeyakumar Vijeyakumar; Sakthisudhan Sakthisudhan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.

Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator Sanket Dessai; Sandeep G.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.

Thermal Analysis of Fair Scheduling in Real-time Embedded Systems Tayyaba Bokhari; Sajjad Haider Shami; Farhan Haseeb
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.

Universal Automobile Headlight Control Module for High Beam Adaptation during Night Vision Travel an Embedded Design Approach M. Subramania Siva; G. Jeyakumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

Road accidents during night travel increases day by day and vision impairment due to high beam contributes to the majority of the total fatalities. Headlights of vehicles pose a great danger during night driving. [1] The drivers of most vehicles use high/bright beam while driving at night. This causes a discomfort to the person travelling from the opposite direction. The driver experiences a sudden glare caused due to the high intense headlight beam from the other vehicle coming towards him from the opposite direction. We are expected to dim the headlight to avoid this glare. This glare causes a temporary blindness to a person resulting in road accidents during the night. To avoid such incidents, an embedded prototype of Automatic Headlight adaptor module is proposed. This embedded module automatically switches the high beam to low beam and returns backs to high beam, thus reducing the sudden glare effect. It also eliminates the requirement of manual switching by the driver to switch back to low beam Universal Headlight adaptor module is a unique solution to achieve the above objective, the headlight intensity of the incoming vehicles causing the glare is automatically attenuated to low beam wirelessly by the nearby vehicles affected by high beam. The interconnected modules at every vehicle independently takes the decision on the head light control of the source vehicle causing the glare by evaluating various parameters like vehicle speed, current GPS location, direction of vehicle etc.

An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications Deepak Prasad; Vijay Nath
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.

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