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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 63 Documents
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Search results for , issue "Vol 14, No 2: May 2019" : 63 Documents clear
Low voltage CMOS power amplifier with integrated analog pre-distorter for BLE 4.0 application Selvakumar Mariappan; Jagadheswaran Rajendran; Norlaili Mohd Noh; Harikrishnan Ramiah; Asrulnizam Abd Manaf; Shukri Korakkottil Kunhi Mohd; Yusman Mohd. Yusof
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp895-902

Abstract

In this paper, a low power consumption linear power amplifier (PA) for Bluetooth Low Energy (BLE) application is presented. An analogue pre-distorter (APD) is integrated to the PA. The APD consist of an active inductor, driver amplifier, and a RC phase linearizer. The PA delivers more than 12dB power gain from 2.4GHz to 2.5GHz. At the center frequency of 2.45GHz, the gain of the PA is 13dB with PAE of 26.7% and maximum output power of 14dBm. The corresponding OIP3 is 27.6dBm. The supply voltage headroom of this PA is 1.8V. The propose APD serves to be a solution to improve the linearity of the PA with minimum trade-off to the power consumption.
Analysis using multiple free space optic channel with amplification to mitigate haze attenuation A.A. Anis; C.B.M. Rashidi; S.A. Aljunid
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp546-554

Abstract

Weather severity has unfavorable effect on FSO transmission performance. The impact could result in poor quality of transmission and communication failure. This paper presents the analysis using multiple free space optic channels with amplification to mitigate haze attenuation. The visibility is progressively reduced due to the attenuation effects, causing the bit error rate to increase. Three designs of FSO system are proposed in this research as they are simulated and analysed thoroughly using Optisys software. The achieved result shows improved performance for Design 3, as the minimum BER achieved is 10-127 when the power received is -26 dBm, and maximum Q-factor of 23.6 at the aperture diameter of 40 cm. It is proved to improve the system efficiently in low visibility condition compared to Design 1 and Design 2. It clearly has shown the superior capabilities of Design 3 to intercept and mitigate the atmospheric attenuation in haze condition as the power loss during transmission also reduced significantly.
Performance evaluation of optical attocells configuration in an indoor visible light communication M.S. M. Gismalla; M.F. L. Abdullah
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp668-676

Abstract

Visible light communication VLC is deemed as futuristic technology applied for both illumination and data communication due to the low-cost energy consumption, long life expectancy, huge bandwidth, and high security compared to radio frequency RF. Uncovered area, minimum signal-to-noise ratio (SNR) and received power results from the non-uniform distribution of small base stations (i.e. Optical attocells) in the room. In this paper, the researchers propose a new LEDs distribution of five optical attocells configuration model in order to optimize the received power distribution and SNR at the center of the room for indoor VLC system. The optical attocells configuration in terms of received power to fill the uncovered area at the center of the room has been investigated. The simulation results showed that the proposed attocells configuration saved 24.9% of the transmitted power. Besides that, the whole room was covered uniformly.  As a result, the received power and SNR are improved.
Characterization of a low consumption wireless sensor node for the intensive transmission of physiological signals Ricardo Yauri; Santiago Rubiños; Juan Grados; Mario Chauca
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp957-965

Abstract

This paper describes the development and implementation of low power consumption wireless sensor nodes for the periodic monitoring of physiological signals with intensive data transmission, using Wi-Fi and ZigBee wireless communication modules, obtaining operation characteristics from the energy point of view that allow to increase the life time of the sensor node. The sensor nodes are designed and built using low energy consumption electronic devices to evaluate their energy performance using current data, transmission time, data transmission period and the relationship with the sensor node's lifetime when transmitting electrocardiographic (ECG), temperature and pulse type physiological signals. The development of this work generates recommendations for the design, development and construction of sensor nodes where the energy consumption of the wireless communication modules is evaluated. In this way, results are obtained that can allow the data transmission period, current consumption and size of data sent to be related to the operating time, defining the operating conditions and wireless technologies that allow the optimization of energy consumption when data is sent to Internet monitoring applications.
Mango ripeness classification system using hybrid technique Muhamad Farid Mavi; Zulkifli Husin; Badlishah Ahmad; Yasmin Mohd Yacob; Rohani S. Mohamed Farook; Wei Keong Tan
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp859-868

Abstract

Nowadays there are many systems develop for agricultural purposes and most system implemented on the use of non-destructive technique not only to classify but also to determine the fruit ripeness. However, most of the studies concentrates using single technique to assess the fruit ripeness. This paper presents the work on mango ripeness classification using hybrid technique. Hybrid stands for mix or combination between two different elements, thus this study combined two different technique that is image processing and odour sensing technique in a single system. Image processing technique are implemented using color image that is HSV image color method to determine the ripeness of fruit based on fruit peel skin through color changes upon ripening. Whereas, odour sensing technique are implemented using sensors array to determine the fruit ripeness through smell changes upon ripening. The “Harumanis” and “Sala” mango was used for sample collection based on two different harvesting condition that is unripe and ripe were evaluated using the image processing and followed by the odour sensor. Support Vector Machine (SVM) is applied as classifier for training and testing based on the data collected from both techniques. The finding shows around 94.69% correct classification using hybrid technique of image processing and odour sensing in a single system.
Android-based automatic detection and measurement system of highway billboard for tax calculation in indonesia Romi Fadillah Rahmat; Sarah Purnamawati; Handra Saito; Muhammad Fariz Ichwan; Tri Murti Lubis
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp877-886

Abstract

Billboards are objects, tools or actions, which based on the characteristics serve its own purpose to earn profits, advertise certain people or service, and to draw public’s attention by placing it in a very strategic place. It has led the government to charge tax on billboards based on its location, dimensions, and viewpoints. Therefore, authorized parties have to be able to ensure the data authenticity of the proposed billboards. One of the obstacles in data verification is the time of billboards measurement process due to its size and height from the ground, based on this problem, and we developed a system which can measure the dimensions of billboards without physically touching it by implementing image processing methods to identify the billboards. The implementation is by measuring the dimensions of the billboards using perspective concept, then calculates the distance between the camera and the object using two-point distance calculation GPS coordinates. The results showed that the distance calculation using the GPS method generated inaccurate values, whereas the systematic distance method generated a result of errors’ range from 0.5 to 25 cm if the image acquisition is performed nearly perpendicular to the object.
Highly sensitive frequency selective surface for structural health monitoring system S. A. Suhaimi; S. N. Azemi; P. J. Soh; C.B.M. Rashidi; A Abdullah Al-Hadi
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp523-528

Abstract

This paper is introduced a passive sensor to detect the performance of the structure using three-dimensional (3D) Frequency Selective Surfaces (FSS). The proposed 3D Circular FSS results are proved behave as passive sensor with changing of sensitivity incident angles to be apply in Structural Health Monitoring (SHM) system. Moreover, this 3D Circular FSS capable to operate without stand to any (DC/AC) power and very low cost in term of installation and maintenance.
FPGA-based embedded architecture for IoT home automation application Chee-Pun Ooi; Wooi-Haw Tan; Soon-Nyean Cheong; Yee-Lien Lee; V. M. Baskaran; Yeong-Liang Low
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp646-652

Abstract

An Internet of Things (IoT) FPGA-based home hub to automate control operations in a home environment was designed and built. The proposed system uses an FPGA home hub as its local analytic engine with an IoT platform to store the sensory data. The FPGA was programmed in Verilog HDL using Quartus II provided by Altera. The WiFi capability of the FPGA was extended through an ESP8266 chip to ease the interfacing with various sensors connected to it. The system can be configured and monitored through a web application coded in JavaScript. Various test cases were carried out on the implemented system at Multimedia University (MMU) Digital Home Lab. The results verified the functionality of the system in triggering real home appliances (i.e. air conditioning unit and lighting) based on multiple sensor nodes without conflicting each other. The ability to allow user to configure the control rules based on the sensory data via web interface hosted using ThingSpeak Plugins is also presented and demonstrated in this project. The base design is utilizing Altera Cyclone IV EP4CE22F17C6N FPGA with 153 I/O pins, which is highly scalable and adaptable to the requirements of home environments. This shows promising application of FPGA in supporting scalable IoT home automation system.
FPGA-based architecture of hybrid multilayered perceptron neural network Lee Yee Ann; P. Ehkan; M. Y. Mashor; S. M. Sharun
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp949-956

Abstract

The HMLP is an ANN similar to the MLP, but with extra weighted connections that connect the input nodes directly to the output nodes. The architecture of the HMLP neural network for implementation on FPGA is proposed. The HMLP architecture is designed to be concurrent to demonstrate the parallel nature of the HMLP where each hidden or output node within the same hidden or output layer of the HMLP can calculate its output independently. The HMLP architecture is designed to be modular as well, such that if modification to a module is necessary, only the specific module need to be modified and all other modules can be retained. This modularity will be especially helpful when different activation function is to be swapped in to replace current activation function. All calculations in the HMLP are performed in floating-point arithmetic. The HMLP architecture is compiled, simulated and finally implemented on the Cyclone V FPGA of DE1-SoC board. The simulation outcome and FPGA outputs showed that the developed HMLP architecture is able to calculate correct output values for all test datasets.
Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture Ng Yen Phing; M.N.Mohd Warip; Phaklen Ehkan; R Badlishah Ahmad; F.W. Zulkefli
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp802-809

Abstract

The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.

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