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All Journal International Journal of Electrical and Computer Engineering Indonesian Journal of Electrical Engineering and Computer Science
Asrulnizam Abd Manaf
Universiti Sains Malaysia
Computer Science & IT Electrical & Electronics Engineering

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A Tunable Ferrofluid-based Polydimethylsiloxane (PDMS) Microchannel Inductor for Ultra High Frequency Applications Ahmad Hafiz Mohamad Razy; Mohd Tafir Mustaffa; Asrulnizam Abd Manaf; Norlaili Mohd Noh
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 2: April 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (683.176 KB) | DOI: 10.11591/ijece.v7i2.pp926-932

Abstract

In this work, a tunable ferrofluid-based polydimethylsiloxane (PDMS) microchannel inductor with high quality factor and high tuning range is proposed. For this project, PDMS is used to create a microchannel with a width and height of 0.53 mm and 0.2 mm respectively. The microchannel is then used to cover the whole design of a solenoid inductor. A solenoid inductor is designed using wire bonding technique where lines of copper and bond wires are used to form a solenoid winding on top of silicon substrate. A light hydrocarbon based ferrofluid EMG 901 660 mT with high permeability of 5.4 is used. The ferrofluid-based liquid is injected into the channel to enhance the performance of a quality factor. A 3D full-wave electromagnetic fields tool, ANSYS HFSS is used in this work to simulate the solenoid inductor. The results obtained in this work gives a quality factor of more than 10 at a frequency range of 300 MHz to 3.3 GHz (Ultra High Frequency range). The highest quality factor is 37 which occurs at a frequency of 1.5 GHz, provides a high tuning range of 112%.
Low voltage CMOS power amplifier with integrated analog pre-distorter for BLE 4.0 application Selvakumar Mariappan; Jagadheswaran Rajendran; Norlaili Mohd Noh; Harikrishnan Ramiah; Asrulnizam Abd Manaf; Shukri Korakkottil Kunhi Mohd; Yusman Mohd. Yusof
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp895-902

Abstract

In this paper, a low power consumption linear power amplifier (PA) for Bluetooth Low Energy (BLE) application is presented. An analogue pre-distorter (APD) is integrated to the PA. The APD consist of an active inductor, driver amplifier, and a RC phase linearizer. The PA delivers more than 12dB power gain from 2.4GHz to 2.5GHz. At the center frequency of 2.45GHz, the gain of the PA is 13dB with PAE of 26.7% and maximum output power of 14dBm. The corresponding OIP3 is 27.6dBm. The supply voltage headroom of this PA is 1.8V. The propose APD serves to be a solution to improve the linearity of the PA with minimum trade-off to the power consumption.
Electronic controlled CMOS inductor with patterned metal ground shields for fine inductance tuning application Nur Syahadah Yusof; Norlaili Mohd Noh; Jagadheswaran Rajendran; Asrulnizam Abd Manaf; Shukri Korakkottil Kunhi Mohd; Yusman Mohd. Yusof; Harikrishnan Ramiah; Mohamed Fauzi Bin Packeer Mohamed
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp937-948

Abstract

This paper is on an inductance fine tuning technique which benefits from the idea of varying the number of metal plates of an inductor’s pattern ground shield (PGS) shorted to ground to change its magnetic fields. This technique is unique because the geometry and physical shape of the inductor remains untouched from its form in the process design kit (PDK) while the inductance is being tuned. The number of metal shields shorted to ground was controlled by an electronic circuit which consists of analog-to-digital converters and active switches. Both Sonnet EM simulator and Cadence Virtuoso were used for the inductor and circuit simulations. From the simulation, it was found that the inductance increased while the Q-factor decreased as more metal shields were shorted to ground. For instance, at 1.6 GHz, the simulated inductance was 8.8 nH when all metals were floated and 9.4 nH when all metals were shorted to ground. On the other hand, the simulated Q-factor was 10.4 when all metals were floated and 9.8 when all metals were shorted to ground. From both simulation and measured results, both inductance and inductance tuning range increased with frequency. From the measured results too, the inductance observed was 9.4 nH at 1.6 GHz, 10.8 nH at 2 GHz, and 13.5 nH at 2.5 GHz when all the metal shields were shorted to ground. The inductance tuning range was 6.2% at 1.6 GHz, 12.5% at 2 GHz, and 20% at 2.5 GHz. The measured results showed good correlation with the simulated results trend, but with smaller value of inductance, inductance tuning range and Q-factor.
Layout Effects on High Frequency and Noise Parameters in MOSFETs Asmaa Nur Aqilah Zainal Badri; Norlaili Mohd Noh; Shukri bin Korakkottil Kunhi Mohd; Asrulnizam Abd Manaf; Arjuna Marzuki; Mohd Tafir Mustaffa
Indonesian Journal of Electrical Engineering and Computer Science Vol 6, No 1: April 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v6.i1.pp88-96

Abstract

This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (fT) and the maximum frequency (fMAX), whereas the noise parameters involved are noise resistance (RN) and the minimum noise figure (NFmin). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (Gm); gate resistance (Rg); effective mobility (μeff); and parasitic capacitances (cgg and cgd). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in fT and fMAX, owing partly to the improvement in Gm, μeff, cgg, cgd and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in fT due to a lower Gm. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for fT, fMAX, Gm and μeff but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of cgg as the transistor becomes narrower, whereas a multi-OD multi-finger may have high Rg and therefore may lead to the increase of fT and fMAX as the transistor becomes narrower. Besides, the doughnut layout style has a higher Gm and fT, leading to larger μeff from the elimination of shallow trench isolation (STI) stress.
Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application Asmaa Nur Aqilah Zainal Badri; Norlaili Mohd Noh; Shukri bin Korakkottil Kunhi Mohd; Asrulnizam Abd Manaf; Arjuna Marzuki; Mohd Tafir Mustaffa; Mohamed Fauzi Packeer Mohamed
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v10.i3.pp925-933

Abstract

Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NFmin) for frequencies below 3 GHz.
Co-Authors Ahmad Hafiz Mohamad Razy Arjuna Marzuki Asmaa Nur Aqilah Zainal Badri Harikrishnan Ramiah Jagadheswaran Rajendran Mohamed Fauzi Bin Packeer Mohamed Mohamed Fauzi Packeer Mohamed Mohd Tafir Mustaffa Mohd Tafir Mustaffa Norlaili Mohd Noh Nur Syahadah Yusof Selvakumar Mariappan Shukri bin Korakkottil Kunhi Mohd Shukri Korakkottil Kunhi Mohd Yusman Mohd. Yusof Yusman Mohd. Yusof