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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 9,174 Documents
 523   524   525   526   527 
Real-Time Video Scaling Based on Convolution Neural Network Architecture S Safinaz; AV Ravi kumar
Indonesian Journal of Electrical Engineering and Computer Science Vol 7, No 2: August 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v7.i2.pp381-394

Abstract

In recent years, video super resolution techniques becomes mandatory requirements to get high resolution videos. Many super resolution techniques researched but still video super resolution or scaling is a vital challenge. In this paper, we have presented a real-time video scaling based on convolution neural network architecture to eliminate the blurriness in the images and video frames and to provide better reconstruction quality while scaling of large datasets from lower resolution frames to high resolution frames. We compare our outcomes with multiple exiting algorithms. Our extensive results of proposed technique RemCNN (Reconstruction error minimization Convolution Neural Network) shows that our model outperforms the existing technologies such as bicubic, bilinear, MCResNet and provide better reconstructed motioning images and video frames. The experimental results shows that our average PSNR result is 47.80474 considering upscale-2, 41.70209 for upscale-3 and 36.24503 for upscale-4 for Myanmar dataset which is very high in contrast to other existing techniques. This results proves our proposed model real-time video scaling based on convolution neural network architecture’s high efficiency and better performance.
QoS Management in WSN-MCN Convergence Network Using Priority Based Traffic Models Anita Swain; Arun Kumar Ray
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 3: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i3.pp1159-1170

Abstract

Technological advancements and increased developments leads to increase the development of hand-held devices which encourage the growth of Machine-to-Machine (M2M) communication. In this context devices belongs to heterogeneous network require a common platform to meet the challenges of data centric wireless services and applications. To satisfy the needs of M2M communication, Mobile Cellular Network (MCN) and Wireless Sensor Network (WSN) converged to a single platform. In this paper two priority models has been proposed with non preemptive priority and preemptive priority to analyze the data traffic at MAC layer of the converged network. The performance matrices are determined to maintain QoS in terms of reduced dropping and blocking probability, waiting time in the queue etc. Finally, the proposed models are compared in terms of QoS factors.
A novel approach of multiplier design based on BCD decoder Salah Alkurwy
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 1: April 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i1.pp38-43

Abstract

A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems      
Active and Reactive Power Scheduling Optimization using Firefly Algorithm to Improve Voltage Stability under Load Demand Variation Mohamad Khairuzzaman Mohamad Zamani; Ismail Musirin; Halim Hassan; Sharifah Azwa Shaaya; Shahril Irwan Sulaiman; Nor Azura Md. Ghani; Saiful Izwan Suliman
Indonesian Journal of Electrical Engineering and Computer Science Vol 9, No 2: February 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v9.i2.pp365-372

Abstract

This paper presents active and reactive power scheduling using firefly algorithm (FA) to improve voltage stability under load demand variation. The study involves the development of firefly optimization engine for power scheduling process involving the active and reactive power for wind generator. The scheduling optimization of wind generator is tested by using IEEE 30-Bus Reliability Test System (RTS). Voltage stability of the system is assessed based in a pre-developed voltage stability indicator termed as fast voltage stability index (FVSI). This study also considers the effects on the loss and voltage profile of the system resulted from the optimization, where the FVSI value at the observed line, minimum voltage of the system and loss were monitored during the load increment. Results obtained from the study are convincing in addressing the scheduling of power in wind generator. Implementation of FA approach to solve power scheduling revealed its flexibility and feasible for solving larger system within different objective functions.This paper presents active and reactive power scheduling using firefly algorithm (FA) to improve voltage stability under load demand variation. The study involves the development of firefly optimization engine for power scheduling process involving the active and reactive power for wind generator. The scheduling optimization of wind generator is tested by using IEEE 30-Bus Reliability Test System (RTS). Voltage stability of the system is assessed based in a pre-developed voltage stability indicator termed as fast voltage stability index (FVSI). This study also considers the effects on the loss and voltage profile of the system resulted from the optimization, where the FVSI value at the observed line, minimum voltage of the system and loss were monitored during the load increment. Results obtained from the study are convincing in addressing the scheduling of power in wind generator. Implementation of FA approach to solve power scheduling revealed its flexibility and feasible for solving larger system within different objective functions.
Robust Visual Multi Target Trackers: A Review Pavan Kumar E; Manojkumar Rajgopal
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 1: October 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i1.pp7-16

Abstract

In this review paper, we address on the state-of-art process with visual object tracking in video surveillance, medical and military applications. In the present scenario number of algorithms and methods are used to track the object in the different scene, a robust visual object tracking remains a critical challenge. The challenges arise due to object motion from frame to frame with a change in appearance, structures, illumination, and occlusion. In this paper, at last, we outline the different algorithms, dataset, strength, and weakness of the different object tracker.
A review of internet of medical things (IoMT) - based remote health monitoring through wearable sensors: a case study for diabetic patients Omar AlShorman; Buthaynah AlShorman; Mahmood Al-khassaweneh; Fahad Alkahtani
Indonesian Journal of Electrical Engineering and Computer Science Vol 20, No 1: October 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v20.i1.pp414-422

Abstract

The latest advances and trends in information technology and communication have a vital role in healthcare industries. Theses advancements led to the internet of medical things (IoMT) which provides a continuous, remote and real-time monitoring of patients. The IoMT architectures still face many challenges related to the bandwidth, communication protocols, big data and data volume, flexibility, reliability, data management, data acquisition, data processing and analytics availability, cost effectiveness, data security and privacy, and energy efficiency. The goal of this paper is to find feasible solutions to enhance the healthcare living facilities using remote health monitoring (RHM) and IoMT. In addition, the enhancement of the prevention, prognosis, diagnosis and treatment abilities using IoMT and RHM is also discussed. A case study of monitoring the vital signs of diabetic patients using real-time data processing and IoMT is also presented. 
Performance Enhancement of NEMO based VANET using Localization Router (LR) to reduce Handoff delays Shaikh Mohammad Ehsanur Rahman; Farhat Anwar; Aisha Hassan Abdalla Hashim
Indonesian Journal of Electrical Engineering and Computer Science Vol 8, No 2: November 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v8.i2.pp511-521

Abstract

Vehicular Ad hoc networks (VANETs) combined with vehicle-to-vehicle and vehicle-to-infrastructure communications can be considered as the most suitable technology to enable ITS (Intelligent Transport System) application bestowed upon travellers with mobility, safety and productivity with human comfort. As a delay sensitive ITS application, handoff delays and packet losses are critical parameters for maintaining seamless connectivity in VANET solution. During handoff, when mobile node (vehicle) is acquiring new CoA (care of address), packets directed towards that node are lost; because it’s old identity is no more valid. So in high speed dynamic vehicular environment the number of frequent handoffs would produce delay beyond the normal limit. Therefore, it is very important to resolve the issues of handoff delay and packet losses in VANET environment. As a solution, a domain based RHD-NV (Reducing Handoff Delay in NEMO based VANET) scheme is proposed in this paper. Number of vehicles moving towards the road constructs a domain where network mobility NEMO-BS protocol is applied. A vehicle is selected as MR (master router) and connected to the RSU (road side unit) to the internet and other vehicles in the domain work as LRs (localization router) and communicate through MR. Simulation tests performed in NS3 (network simulator) and MATLAB SIMULINK demonstrate that using LRs (localization router) in the domain, the number of handoffs and handoff delay are significantly reduced.
Manual clock distribution technique in partitioning stage for multi-FPGA prototyping Salahuddin Savugathali; Muslim Mustapa; Fazrul Faiz Zakaria
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp637-645

Abstract

As the complexity of ASIC/SoC design is increasing along with the number of logic gates, a prototyping process in the verification stage is facing a challenge when the ASIC/SoC design cannot fit into a single FPGA. A solution to prototyping multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. There are various implementation tools and platform available in the market which automates an FPGA-based prototype phase such as Cadence Protium Rapid Prototyping Platform, Synopsys and S2C. In this paper, Synopsys protocompiler tool will be used to perform the prototyping process of the large 4 core CPU based circuit into the HAPS-80 FPGA platform. This paper will be focusing on the partition requirement needed to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will resulting to the failure in routing stage due to the congestion error. In this paper, two techniques are used, which is automatic clock replication by the Synopsys Protocompiler tool and our proposed technique which is Manual Clock Distribution technique to solve the presence of the cut clock, so that the circuit is able to meet the partition requirement to complete the prototyping process into multi-FPGA. Obtained result from the proposed technique showing that prototyping the large SoC circuit into the multi-FPGA platform has met the specification by eliminating 100% presence of cut clock.
An Improved Criterion for Induced Stability of Fixed-Point Digital Filters with Saturation Arithmetic Priyanka Kokil; Xavier Arockiaraj S
Indonesian Journal of Electrical Engineering and Computer Science Vol 4, No 1: October 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v4.i1.pp65-72

Abstract

This paper establishes a criterion for the induced  stability of fixed-point state-space digital filters with saturation nonlinearities and external interference. The criterion is established in a linear matrix inequality (LMI) setting, and therefore, computationally tractable. The criterion turns out to be an improvement over a previously reported criterion. A comparison of the presented criterion with existing criterion is made. Numerical examples are given to demonstrate the usefulness of the proposed approach.
Effect of Deposition Temperature on Self-Catalyzed ZnO Nanorods via Chemical Vapour Deposition Method Shafinaz Sobihana Shariffudin; Puteri Sarah Mohamad Saad; Hashimah Hashim; Mohamad Hafiz Mamat
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 1: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v11.i1.pp209-214

Abstract

The morphological, structural, optical and electrical properties of ZnO nanorods are investigated as a function of deposition temperature. The ZnO nanorods were grown on ZnO seed catalyst layer at temperatures between 750oC – 825oC using thermal chemical vapour deposition method.  Sample deposited at 825oC showed the highest crystalline orientation. The FE-SEM micrographs and the intense peak along (002) direction in the XRD spectra of this sample implied that the nanorods possess c-axis orientation. PL spectra showed two common ZnO peaks which centered at 380 nm and 540 nm. Two-point probe I-V measurement revealed ohmic behaviour with the gold metal contact, whereby the current increase with the deposition temperature.

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