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Alde Alanda
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alde@pnp.ac.id
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Kampus Limau Manis
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Kota padang,
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INDONESIA
International Journal of Advanced Science Computing and Engineering
Published by Society of Visual Informatics
ISSN : 27147533     EISSN : 27147533     DOI : https://doi.org/10.30630/ijasce
Core Subject : Science, Engineering,
Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering
The journal scopes include (but not limited to) the followings: Computer Science : Artificial Intelligence, Data Mining, Database, Data Warehouse, Big Data, Machine Learning, Operating System, Algorithm Computer Engineering : Computer Architecture, Computer Network, Computer Security, Embedded system, Coud Computing, Internet of Thing, Robotics, Computer Hardware Information Technology : Information System, Internet & Mobile Computing, Geographical Information System Visualization : Virtual Reality, Augmented Reality, Multimedia, Computer Vision, Computer Graphics, Pattern & Speech Recognition, image processing Social Informatics: ICT interaction with society, ICT application in social science, ICT as a social research tool, ICT education
Arjuna Subject : Ilmu Komputer (semua kategori) - Ilmu Komputer (Lain-Lain)
Articles 5 Documents
 1 
Search results for , issue "Vol. 3 No. 1 (2021)" : 5 Documents clear
A Review for the Mechanism of Research Productivity Enhancement in the Higher Education Institution Sanmorino, Ahmad; Karimah, Fitrah
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (294.333 KB) | DOI: 10.62527/ijasce.3.1.43

Abstract

The main purpose of this review is to find out the mechanism of research productivity enhancement proposed by each researcher in the papers they have published. The availability of these various mechanisms raises the desire of the authors to compare each mechanism. The focus of the review lies in the mechanism, characteristics, source of data, and evaluation methods used by each researcher. The review then jumps to the results obtained by each mechanism. The author also compares the types of data used by each researcher and the parties involved in the mechanism. There are some differences in the use of terminology between one to another mechanism, but in essence, it has the same goal, research productivity enhancement.
TF-IDF Implementation for Similarity Checker on The Final Project Title Meidelfi, Dwiny; Yulherniwati, -; Rahmayuni, Indri; Hidayat, Taufik; Chandra, Dikky
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (477.858 KB) | DOI: 10.62527/ijasce.3.1.3

Abstract

Students of the Software Engineering Technology Study Program, Department of Information Technology, Politeknik Negeri Padang, is required to compile a final project to complete their study period. In the implementation of the final project, several parties have involved such as the KBK team whose job is to check whether the proposed title is appropriate or not. The main issue undertaken by KBK is whether the title submitted has been used or not. The method used by KBK in checking the availability of titles was by looking at the titles of the final projects that have been submitted by previous students. The examination process carried out by the KBK, it took a long time. By utilizing the Cosine Similarity algorithm and TF-IDF, it is expected that it will make it easier for KBK to check the availability of final project titles. Cosine similarity is a method used to calculate the degree of similarity between 2 or more documents. While the TF-IDF Algorithm is a method used to weight a word in a document. The object of testing in this study was the title of the student’s final project. The process of calculating the level of similarity of documents started from the preprocessing stage, then proceeds with weighting using TF-IDF and calculating the level of similarity used the Cosine Similarity algorithm. The final result found that system could calculate the degree of similarity of the title of the student’s final project. From the results of testing the process of calculating the degree of similarity of titles using the cosine similarity algorithm can be undertaken quickly.
VLSI Architecture for Smart and Precision Agriculture Using Sensors Vedulla, Tarun.; Reddy, Y. Maheswar; Kalyan, Achyuta; Jenila, R.
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (782.746 KB) | DOI: 10.62527/ijasce.3.1.32

Abstract

World population has almost doubled during the last century increasing dramatically the need for food to support the population over 7 billion persons. Precision agriculture is a type of innovative agriculture, based on new technologies, which aims to streamline the agricultural process. Parameters such as temperature, humidity, soil characteristics, and nutrients all play a role in plant development. Numerous sensors are available to measure the environmental factors and depending on datum, the devices monitor and control the parameter changes for each crop. Some existing technologies are more complex and very complicated for farmers to implement. The main goal of this project is to produce precision agriculture-based grid with high performance and low energy consumption.
Forecasting Enrolment Data of Surigao del Sur State University, Philippines using Regression Analysis and Multiplicative Decomposition Model Maliberan, Esmael V.
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (309.202 KB) | DOI: 10.62527/ijasce.3.1.26

Abstract

The study endeavored to predict the number of students who will enroll in Surigao del Sur State University using the historic data from 2010-2015. It was accomplished to utilize two existing methods to form its model in forecasting the enrolment data of the University. To project the number of students enrolled at the university, regression analysis, and a multiplicative decomposition model is used. The Mean Absolute Percentage Error (MAPE) of the forecasted enrolment data was 3.10 percent, according to the results. This only demonstrated that the estimated data were similar to the actual data, implying that it is accurate. The predicted enrolment data can be used to support decision-making and as an input to the University Development Plan.
FPGA Implementation of High Speed and Area Efficient Three Operand Binary Adder Azeez, Saba; Rangaree, Pankaj
International Journal of Advanced Science Computing and Engineering Vol. 3 No. 1 (2021)
Publisher : SOTVI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (422.642 KB) | DOI: 10.62527/ijasce.3.1.34

Abstract

Three operand binary adder is the basic functional unit to perform the pseudorandom bit generator algorithms and in various cryptography. The basic method used to perform the three-operand binary addition is carry save adder, which leads to high delay. For this a parallel prefix two operand adder such as Han-Carlson adder is used to reduce the delay but increases the hardware architecture i.e., area increases. To overcome this disadvantage, we need a new area efficient and high-speed adder architecture to be proposed using pre compute bitwise addition followed by carry prefix computation logic to perform three operand binary adder which reduces delay and area efficiently. This method is the proposed method and implemented on the FPGA device. A newly designed three operand binary adder is shown and is implemented in MDCLCG. The results of 16 bit and 32-bit three operand adder will be shown and this proposed method is applied on Modified Dual CLCG. The Carry-Save-Adder architecture used in 32-bit MDCLCG is replaced by the proposed architecture. The design is prototyped on a commercially available FPGA platform to validate the design on silicon chip.

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