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All Journal International Journal of Electrical and Computer Engineering Journal of ICT Research and Applications
Nur Ahmadi
Institut Teknologi Bandung
Computer Science & IT Electrical & Electronics Engineering

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Empirical Mode Decomposition (EMD) Based Denoising Method for Heart Sound Signal and Its Performance Analysis Amy Hamidah Salman; Nur Ahmadi; Richard Mengko; Armein Z. R. Langi; Tati L. R. Mengko
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 5: October 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (812.783 KB) | DOI: 10.11591/ijece.v6i5.pp2197-2204

Abstract

In this paper, a denoising method for heart sound signal based on empirical mode decomposition (EMD) is proposed. To evaluate the performance of the proposed method, extensive simulations are performed using synthetic normal and abnormal heart sound data corrupted with white, colored, exponential and alpha-stable noise under different SNR input values. The performance is evaluated in terms of signal-to-noise ratio (SNR), root mean square error (RMSE), and percent root mean square difference (PRD), and compared with wavelet transform (WT) and total variation (TV) denoising methods. The simulation results show that the proposed method outperforms two other methods in removing three types of noises.
An SoC Architecture for Real-Time Noise Cancellation System Using Variable Speech PDF Method Trio Adiono; Aditya F. Ardyanto; Nur Ahmadi; Idham Hafizh; Septian G. P. Putra
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 6: December 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (572.191 KB) | DOI: 10.11591/ijece.v5i6.pp1336-1346

Abstract

This paper presents the architecture and implementation of system-on-chip (SoC) for realtime noise cancellation system which exploits variable speech probability density function (PDF) and maximum a posteriori (MAP) estimation rule as noise cancelling algorithm. The hardware software co-design approach is employed to achieve real-time performance while considering ease of implementation and design flexibility. The software module utilizes LEON SPARC-v8 and FPU co-prosessor as processing unit. The AMBA based Hanning Filter and FFT/IFFT are utilized as processing accelerator modules to increase system performance. The FFT/IFFT module employs custom Radix-2^2 Single Delay Feedback (R2^2SDF). In order to deliver high data transfer rate between buffer and hardware accelerators, the DMA controller is incorporated. The overall system implementation utilizes 18,500 logic elements and consumes 21.87 kB of memory. The system takes only 0.69 ms latency which is appropriate for real-time application. An FPGA Altera DE2-70 is used for prototyping with both algorithms and the noise cancellation function have been verified.
An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA Trio Adiono; Rian Ferdian; Febri Dawani; Imran Abdurrahman; Rachmad Vidya Wicaksana Putra; Nur Ahmadi
Journal of ICT Research and Applications Vol. 12 No. 1 (2018)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.res.appl.2018.12.1.5

Abstract

Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.
Co-Authors Aditya F. Ardyanto Amy Hamidah Salman Armein Z. R. Langi Dawani, Febri Idham Hafizh Imran Abdurrahman Rachmad Vidya Wicaksana Putra Richard Mengko Septian G. P. Putra Tati L. R. Mengko Trio Adiono