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Desain Sistem Rumah Cerdas berbasis Topologi Mesh dan Protokol Wireless Sensor Network yang Efisien Adiono, Trio; Putra, Rachmad Vidya Wicaksana; Fathany, Maulana Yusuf; Adijarto, Waskita
INKOM Journal Vol 9, No 2 (2015)
Publisher : Pusat Penelitian Informatika - LIPI

Dalam publikasi ini, kami mengusulkan sistem rumah cerdas berdasarkan dua pendekatan. Pendekatan pertama adalahÂ arsitektur bertopologi mesh dan yang kedua adalah protokol Wireless Sensor Network (WSN) yang efisien. Sistem iniÂ memiliki dua lingkungan kerja, indoor dan outdoor. Lingkungan indoor menggunakan sistem WSN, sedangkanÂ lingkungan luar menggunakan sistem internet-cloud. Skema ini dikenal sebagai Internet-of-Things (IoT). LingkunganÂ indoor dan outdoor terhubung satu sama lain dengan menggunakan suatu jembatan penghubung. Sistem WSN dibentukÂ dari komponen-komponen WSN yang menggunakan topologi mesh. Setiap komponen dari WSN dirancang untuk mengimplementasikan protokol data efisien yang diusulkan. Untuk lingkungan outdoor, sistem internet-cloud yang adaÂ adalah infrastruktur utama. Dengan demikian, sistem rumah cerdas ini dapat dipantau dan dikendalikan dari ponselÂ cerdas, kapan saja dan di mana saja, selama akses mobile data tersedia. Untuk evaluasi sistem, beberapa tes telahdilakukan untuk mendapatkan profil sistem.

Rapid Prototyping Methodology of Lightweight Electronic Drivers for Smart Home Appliances Trio Adiono; Rachmad Vidya Wicaksana Putra; Maulana Yusuf Fathany; Braham Lawas Lawu; Khilda Afifah; Muhammad Husni Santriaji; Syifaul Fuada
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 5: October 2016
Publisher : Institute of Advanced Engineering and Science

Many researches have been conducted in smart home topic. Mostly, they discussed on the specific aspect of application. On the other side, many applications still can be explored and attached into the system. Several main challenges in designing the application devices are system complexity, reliability, user friendliness, portability, and low power consumption. Thus, design of electronic driver is one of the key elements for overcoming these challenges. Moreover, the drivers have to comply the rules of smart home system, data protocol, and application purpose. Hence, we propose a rapid prototyping methodology on designing lightweight electronic drivers for smart home appliances. This methodology consists of three main aspects, namely smart home system understanding, circuitry concept, and programming concept. By using this method, functional and lightweight drivers can be achieved quickly without major changes and modifications in home electrical system. They can be remotely controlled and monitored anytime and from anywhere. For prototyping, we design several drivers to represent common electronic and mechanical based applications. Experimental results prove that the proposed design methodology can achieve the research target.

Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE Trio Adiono; Ahmad Zaky Ramdani; Rachmad Vidya Wicaksana Putra
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018
Publisher : Institute of Advanced Engineering and Science

Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.

Noise and Bandwidth Consideration in Designing Op-Amp Based Transimpedance Amplifier for VLC Trio Adiono; Rachmad Vidya Wicaksana Putra; Syifaul Fuada
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

In a visible light communication (VLC) system, there are many modules involved. One of the important modules is Transimpedance Amplifier (TIA) that resides in the analog front-end receiver (Rx-AFE). TIA is responsible for performing signal conversion from current signal, which is provided from the photodiode (PD) to voltage signal. It is the reason why the TIA should be operating in low noise condition and wide bandwidth of frequency. These will enable a flexible coverage of the VLC system in performing its signal processing. Hence, in this research, we provide considerations of the noise and frequency bandwidth analysis in designing TIA to cope with the required design specification of a VLC system.

Noise and Bandwidth Consideration in Designing Op-Amp Based Transimpedance Amplifier for VLC Trio Adiono; Rachmad Vidya Wicaksana Putra; Syifaul Fuada
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

In a visible light communication (VLC) system, there are many modules involved. One of the important modules is Transimpedance Amplifier (TIA) that resides in the analog front-end receiver (Rx-AFE). TIA is responsible for performing signal conversion from current signal, which is provided from the photodiode (PD) to voltage signal. It is the reason why the TIA should be operating in low noise condition and wide bandwidth of frequency. These will enable a flexible coverage of the VLC system in performing its signal processing. Hence, in this research, we provide considerations of the noise and frequency bandwidth analysis in designing TIA to cope with the required design specification of a VLC system.

Desain Sistem Rumah Cerdas berbasis Topologi Mesh dan Protokol Wireless Sensor Network yang Efisien Trio Adiono; Rachmad Vidya Wicaksana Putra; Maulana Yusuf Fathany; Waskita Adijarto
INKOM Journal Vol 9, No 2 (2015)
Publisher : Pusat Penelitian Informatika - LIPI

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.14203/j.inkom.429

Dalam publikasi ini, kami mengusulkan sistem rumah cerdas berdasarkan dua pendekatan. Pendekatan pertama adalahÂ arsitektur bertopologi mesh dan yang kedua adalah protokol Wireless Sensor Network (WSN) yang efisien. Sistem iniÂ memiliki dua lingkungan kerja, indoor dan outdoor. Lingkungan indoor menggunakan sistem WSN, sedangkanÂ lingkungan luar menggunakan sistem internet-cloud. Skema ini dikenal sebagai Internet-of-Things (IoT). LingkunganÂ indoor dan outdoor terhubung satu sama lain dengan menggunakan suatu jembatan penghubung. Sistem WSN dibentukÂ dari komponen-komponen WSN yang menggunakan topologi mesh. Setiap komponen dari WSN dirancang untuk mengimplementasikan protokol data efisien yang diusulkan. Untuk lingkungan outdoor, sistem internet-cloud yang adaÂ adalah infrastruktur utama. Dengan demikian, sistem rumah cerdas ini dapat dipantau dan dikendalikan dari ponselÂ cerdas, kapan saja dan di mana saja, selama akses mobile data tersedia. Untuk evaluasi sistem, beberapa tes telahdilakukan untuk mendapatkan profil sistem.

Noise and Bandwidth Consideration in Designing Op-Amp Based Transimpedance Amplifier for VLC Trio Adiono; Rachmad Vidya Wicaksana Putra; Syifaul Fuada
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

In a visible light communication (VLC) system, there are many modules involved. One of the important modules is Transimpedance Amplifier (TIA) that resides in the analog front-end receiver (Rx-AFE). TIA is responsible for performing signal conversion from current signal, which is provided from the photodiode (PD) to voltage signal. It is the reason why the TIA should be operating in low noise condition and wide bandwidth of frequency. These will enable a flexible coverage of the VLC system in performing its signal processing. Hence, in this research, we provide considerations of the noise and frequency bandwidth analysis in designing TIA to cope with the required design specification of a VLC system.

A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm Rachmad Vidya Wicaksana Putra; Rella Mareta; Nurfitri Anbarsanti; Trio Adiono
Journal of ICT Research and Applications Vol. 6 No. 2 (2012)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.2012.6.2.3

In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter -adders to substitute multiplier s. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz).

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm Rachmad Vidya Wicaksana Putra; Trio Adiono
Journal of ICT Research and Applications Vol. 10 No. 1 (2016)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.res.appl.2016.10.1.5

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA Trio Adiono; Rian Ferdian; Febri Dawani; Imran Abdurrahman; Rachmad Vidya Wicaksana Putra; Nur Ahmadi
Journal of ICT Research and Applications Vol. 12 No. 1 (2018)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.res.appl.2018.12.1.5

Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.

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