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This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS) International Journal of Reconfigurable and Embedded Systems (IJRES) TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics Proceeding of the Electrical Engineering Computer Science and Informatics Indonesian Journal of Electrical Engineering and Computer Science
Aiman Zakwan Jidin
Universiti Teknikal Malaysia Melaka
Computer Science & IT Control & Systems Engineering Economics, Econometrics & Finance Electrical & Electronics Engineering

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Review on Adjustable Speed Drive Techniques of Matrix Converter Fed Three-Phase Induction Machine Arsyad Cahya Subrata; Tole Sutikno; Aiman Zakwan Jidin; Auzani Jidin
Proceeding of the Electrical Engineering Computer Science and Informatics Vol 5: EECSI 2018
Publisher : IAES Indonesia Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (808.702 KB) | DOI: 10.11591/eecsi.v5.1719

Abstract

Adjustable Speed Drive (ASD) fed Matrix Converter is an interesting topic and is widely discussed in several articles. ASD provides many advantages, especially in the industrial sector because it increases work efficiency so as to reduce production costs. The induction machines construction is sturdy and its relatively inexpensive maintenance makes it more desirable in industrial process applications. Whereas the Matrix Converter (MC) construction without dc-link capacitors makes it more compact compared to conventional converters. This article discussed the ASD control modulation technique by using MC on a three-phase induction motor.
Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices Mohd Syafiq Mispan; Aiman Zakwan Jidin; Muhammad Raihaan Kamarudin; Haslinah Mohd Nasir
Indonesian Journal of Electrical Engineering and Computer Science Vol 25, No 1: January 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v25.i1.pp105-112

Abstract

An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF.
Proof of concept for lightweight PUF-based authentication protocol using NodeMCU ESP8266 Mohd Syafiq Mispan; Aiman Zakwan Jidin; Muhammad Raihaan Kamaruddin; Haslinah Mohd Nasir
Indonesian Journal of Electrical Engineering and Computer Science Vol 24, No 3: December 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v24.i3.pp1392-1398

Abstract

Wireless sensor node is the foundation for building the next generation of ubiquitous networks or the so-called internet of things (IoT). Each node is equipped with sensing, computing devices, and a radio transceiver. Each node is connected to other nodes via a wireless sensor network (WSN). Examples of WSN applications include health care monitoring, and industrial monitoring. These applications process sensitive data, which if disclosed, may lead to unwanted implications. Therefore, it is crucial to provide fundamental security services such as identification and authentication in WSN. Nevertheless, providing this security on WSN imposes a significant challenge as each node in WSN has a limited area and energy consumption. Therefore, in this study, we provide a proof of concept of a lightweight authentication protocol by using physical unclonable function (PUF) technology for resource-constrained wireless sensor nodes. The authentication protocol has been implemented on NodeMCU ESP8266 devices. A server-client protocol configuration has been used to verify the functionality of the authentication protocol. Our findings indicate that the protocol used approximately 7% of flash memory and 48% of static random-access memory (SRAM) in the sensor node during the authentication process. Hence, the proposed scheme is suitable to be used for resource-constrained IoT devices such as WSN.
A review of field-programmable gate array-based biomedical signal processing for public health applications Tole Sutikno; Aiman Zakwan Jidin; Lina Handayani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp320-338

Abstract

Biomedical signal processing is essential for modern diagnostics, monitoring, and preventive healthcare in public health and mobile health (mHealth) systems. Signals such as electroencephalography (EEG), electromyography (EMG), and heart rate variability (HRV) offer vital insights into brain, muscle, and cardiovascular health. However, achieving real-time, energy-efficient, and scalable processing remains challenging for conventional hardware such as central-processing units (CPUs), graphics-processing units (GPUs), and application-specific integrated circuits (ASICs). Field-programmable gate arrays (FPGAs) provide a promising alternative through their reconfigurability, parallelism, and adaptability to dynamic biomedical workloads. This review examines FPGA-based implementations for EEG, EMG, and HRV processing, focusing on key metrics including latency, throughput, and power efficiency. It also discusses design strategies such as low-power optimization, hardware–software co-design, and FPGA-based machine learning acceleration, with attention to data integrity and security in medical contexts. Integration with wearable, portable, and telemedicine platforms is explored, alongside comparative analyses with traditional computing architectures. The paper identifies challenges in power–performance trade-offs, design complexity, and clinical validation, and highlights emerging directions such as artificial intelligence (AI)-driven FPGA platforms, neuromorphic design, and sustainable low-cost solutions for large-scale health monitoring. Overall, FPGA-based biomedical signal processing emerges as a foundation for intelligent, efficient, and accessible next-generation public-health technologies.
Energy-efficient reconfigurable architectures for Edge AI in healthcare IoT: trends, challenges, and future directions Tole Sutikno; Aiman Zakwan Jidin; Lina Handayani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp1-20

Abstract

The integration of Edge artificial intelligence (AI) with internet of things (IoT) technologies is transforming healthcare applications, including wearable monitoring, telemedicine, and implantable medical devices, by enabling low-latency and intelligent data processing close to patients. However, stringent requirements on energy efficiency, reliability, real-time responsiveness, and data privacy continue to hinder scalable and long-term deployment in resource-constrained healthcare environments. Energy-efficient reconfigurable architectures—such as field-programmable gate arrays (FPGAs), coarse-grained reconfigurable arrays (CGRAs), and emerging memory-centric and heterogeneous platforms—have emerged as promising solutions to address these challenges by balancing flexibility, adaptability, and power efficiency. This review systematically examines recent advances in reconfigurable Edge AI architectures for healthcare IoT, highlighting key trends in hardware–software co-design, AI-assisted design automation, memory-centric optimization, and domain-specific overlays. It further identifies critical challenges, including energy–performance trade-offs, runtime reconfiguration overheads, security and privacy vulnerabilities, limited standardization, and reliability concerns in dynamic clinical settings. Finally, future research directions are outlined, emphasizing self-optimizing and context-aware architectures, secure and trustworthy reconfiguration mechanisms, unified frameworks for heterogeneous healthcare workloads, and sustainable, carbon-aware edge computing. Collectively, this review positions energy-efficient reconfigurable architectures as a foundational enabler for next-generation Edge AI in IoT-enabled healthcare systems.
Home grocery listing hardware system and mobile application with speech recognition feature Mohamad Faris Eizlan Suhaimi; Aiman Zakwan Jidin; Haslinah Mohd Nasir; Mohd Haidar Md Hamzah; Mohd Syafiq Mispan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp109-118

Abstract

A home grocery list is a crucial aspect of household management that ensures sufficient kitchen supplies. The classic pen-and-paper grocery list is ineffective since it is time-consuming and prone to human error. Therefore, in this study, we proposed a microcontroller-based home grocery listing system using a barcode scanner and speech recognition. The proposed system consists of hardware and a mobile application. The main hardware components are the ESP32-S3 microcontroller, MH-ET barcode scanner v3.0, 20×4 LCD, and 2.4 GHz wireless keyboard. The mobile application is developed using the MIT App Inventor. Through the hardware, the system receives user input from barcode scanning or manual data entry using the keyboard. The data captured using a barcode scanner or keyboard is stored in the memory. Subsequently, the data is transmitted to the mobile application of the home grocery listing system via WiFi. Moreover, the mobile application is also equipped with user input via speech recognition and manual data entry using the keyboard. Hence, users have the flexibility to input the grocery list using four methods within the system. The developed home grocery listing system gives a new, satisfying experience to the users and a convenient way for them to make a home grocery list.
A comprehensive review of memory BIST algorithms for SRAM static fault detection Aiman Zakwan Jidin; Razaidi Hussin; Mohd Syafiq Mispan; Lee Weng Fook; Loh Wan Ying
Indonesian Journal of Electrical Engineering and Computer Science Vol 43, No 2: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v43.i2.pp400-412

Abstract

Memory built-in self-test (MBIST) has become an essential design-for testability technique for ensuring the reliability and quality of embedded memories in modern integrated circuits. The effectiveness of an MBIST implementation is largely determined by its test algorithm, which defines the sequence of memory operations, directly influencing both test complexity and fault coverage. Designing an efficient test algorithm requires balancing low test complexity with comprehensive fault detection. This paper presents a comprehensive review of MBIST test algorithms for static fault detection in static random-access memory (SRAM). The review first summarizes the characteristics of major SRAM static faults and their corresponding detection requirements. It then compares representative test algorithms in terms of test sequence, computational complexity, fault coverage, and design methodology. Furthermore, the evolution of MBIST test algorithm development is discussed, ranging from conventional ad hoc approaches to enhanced algorithms derived from existing March tests. The comparative analysis indicates that an 18N-complexity test algorithm is generally required to achieve complete detection of all unlinked static faults in SRAM, whereas optimized 14N-complexity algorithms provide an effective trade-off between test time and fault coverage. Finally, the review identifies current research challenges, including efficient detection of dynamic and linked memory faults and the development of MBIST algorithms for emerging memory technologies such as magnetic random-access memory (MRAM), highlighting promising directions for future research.
Co-Authors A. Shamsul Rahimi A. Subki Ahmad Hafizzudin Mustafa Ahmad Nizammuddin Muhammad Mustafa Auzani Jidin Fazlli Patkar Hafez Sarkawi Haslinah Mohd Nasir Huzainirah Ismail Irna Nadira Mahzan Lee Weng Fook Lina Handayani Loh Wan Ying Mohamad Faris Eizlan Suhaimi Mohd Faizal Zulkifli Mohd Haidar Md Hamzah Mohd Syafiq Mispan Mohd Zaidi Mohd Tumari Muhammad Raihaan Kamaruddin Muhammad Raihaan Kamarudin Nik Rumzi Nik Idris Noor Azida Noor Azlan Noor Mohd Ariff Brahin Norain Rahim Norfadzlia Mohd Yusof Razaidi Hussin Siti Asma Che Aziz Subrata, Arsyad Cahya Tole Sutikno Wan Haszerila Wan Hassan Wan Norhisyam Abd Rashid